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Observer
Observer
626 Views
Registered: ‎12-16-2015

40G Ethernet Subsystem low latency mode

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Hi,

I am just making simulation with 40G Ethernet Subsytem IP Core. I red the datasheet, it is written that low latency mode is available. Then I saw below section. And It is written that  153ns latency occurs in this clocking mode.

image.png

 

Then I opened the Open IP Example Design and tracked the clock signals. I made some changes with clocks but in simulation, again there is 304ns between tx_axis_tvalid and rx_axis_tvalid. How can I reduce latency from 304ns to 153ns.

 

Thanks.

 

Samet

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Xilinx Employee
Xilinx Employee
538 Views
Registered: ‎05-01-2013

The number doesn't include GT

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Xilinx Employee
Xilinx Employee
539 Views
Registered: ‎05-01-2013

The number doesn't include GT

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Observer
Observer
513 Views
Registered: ‎12-16-2015
Thanks a lot. Should I understand that in simulation minimum latency is 304ns and it includes GT.
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Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎05-01-2013

Yes.