AXI 1G/2.5G Ethernet Subsystem / AXI Direct Memory Access Buffer Zeroize Function on Reset?
I am working on a design that requires the ability to zeroize, or in general, flush out any buffer on command to prevent any sensitive data leakage in the event the device becomes compromised. Running a MBIST cycle is also acceptable.
PG138 and PG021 for the AXI 1G/2.5G Ethernet Subsystem and AXI Direct Memory Access IP respectively have sections dedicated to reset behavior, but they both focus on how many clock cycles must elapse before accessibility is restored, rather than what is actually occurring inside the IP during a reset condition.
When the IP are reset, are the buffers cleared out, or an MBIST function ran? Otherwise, when the IP comes out of reset, could there still be left over data on the buffers from before the reset was triggered? All documented recommendations regarding the minimum number of clock cycles to pass after a reset event will be observed.