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d93
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Registered: ‎06-25-2021

AXI 1G/2.5G Ethernet Subsystem Example Design not working in Vivado 2021.1

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While trying to simulate a custom design containing the AXI 1G/2.5G Ethernet Subsystem in Vivado 2021.1, it seems the Ethernet core is stuck and has many signals set to high impedance Z. I have tried the example designs of the Ethernet Subsystem instead and compared the waveforms / simulation outputs between Vivado 2021.1 and 2020.2 and everything is working fine under the older version 2020.2.
The example designs were not modified and simulation was launched directly after opening the designs. It seems this is almost exactly the same problem as in this post some years ago. I have also launched simulation of the example design with Modelsim 2020.2 but the problems persist.

Here is the result from Vivado 2021.1:

axi_eth_example_design_sim_2021_1.png

And here is the working result from Vivado 2020.2:

axi_eth_example_design_sim_2020_2.png


Is there a possible fix for this problem? I also tried speeding up the simulation with the simulation option "-d SIM_SPEED_UP" for xvlog and I also tried to fix this bug by setting the SIMULATION_MODE design paramter of the AXI 1G/2.5G Ethernet Subsystem to "true" - both things did not change anything and the 'Z'-signals remain.

axi_eth_example_design_sim_2021_1.png
axi_eth_example_design_sim_2020_2.png
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nanz
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Registered: ‎08-25-2009

Hi @d93 ,

I've got an update that - Main wrapper for axi ethernet is in verilog but certain subcores such as axi ethernet buffer, binary counter and shift ram are generated in VHDL irrespective of language. In addition this encrypted rtl (<core>_rfs) is in vhdl for most subcores. So its not possible to run simulation with language set to verilog.

Hope this answers.


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View solution in original post

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nanz
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Registered: ‎08-25-2009

Hi @d93 ,

Could you please upload your XCI file? So I could try to reproduce the issue locally. Thanks. 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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d93
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Registered: ‎06-25-2021

Of course. I have attached the *.xci file from the example design from Vivado 2021.1. Since I am getting some error on content/file extensions mismatch while uploading, I have appended the .xml extension.

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nanz
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Registered: ‎08-25-2009

Hi @d93 ,

I used your xci in 2021.1 to generate the IP. Then I opened example design. After, I set SIMULATION_MODE:

set_property CONFIG.SIMULATION_MODE {1} [get_ips axi_ethernet_0]

It seems working for me in simulation:

nanz_0-1624640315376.png

Here is the output from the console:

*************************************************************************************

run all
** Note: Resetting core...
Info: [Unisim IDELAYCTRL-1] RST simulation behaviour for SIM_DEVICE ULTRASCALE may not match hardware behaviour when I/ODELAY DELAY_FORMAT = TIME if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide. Instance: axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.mac.inst.tri_mode_ethernet_mac_idelayctrl_common_i
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.RCV_INTFCE_I.RX_DP_MEM_IF_I.I_RXD_MEM.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /axi_ethernet_0_demo_tb/dut/axi_ethernet_0_support/U0_axi_ethernet_0/inst/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/xpm_memory_base_inst/Initial296_3 Scope: axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.RCV_INTFCE_I.RX_DP_MEM_IF_I.I_RXD_MEM.xpm_memory_base_inst.config_drc File: /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 492
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.RCV_INTFCE_I.RX_DP_MEM_IF_I.I_RXS_MEM.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /axi_ethernet_0_demo_tb/dut/axi_ethernet_0_support/U0_axi_ethernet_0/inst/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXS_MEM/xpm_memory_base_inst/Initial296_27 Scope: axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.RCV_INTFCE_I.RX_DP_MEM_IF_I.I_RXS_MEM.xpm_memory_base_inst.config_drc File: /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 492
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.TX_INTFCE_I.TX_MEM_INTERFACE.TXD_MEM.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /axi_ethernet_0_demo_tb/dut/axi_ethernet_0_support/U0_axi_ethernet_0/inst/eth_buf/U0/TX_INTFCE_I/TX_MEM_INTERFACE/TXD_MEM/xpm_memory_base_inst/Initial296_100 Scope: axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.TX_INTFCE_I.TX_MEM_INTERFACE.TXD_MEM.xpm_memory_base_inst.config_drc File: /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 492
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.TX_INTFCE_I.TX_MEM_INTERFACE.TXC_MEM.xpm_memory_base_inst.config_drc 0
Time: 1 ps Iteration: 0 Process: /axi_ethernet_0_demo_tb/dut/axi_ethernet_0_support/U0_axi_ethernet_0/inst/eth_buf/U0/TX_INTFCE_I/TX_MEM_INTERFACE/TXC_MEM/xpm_memory_base_inst/Initial296_3 Scope: axi_ethernet_0_demo_tb.dut.axi_ethernet_0_support.U0_axi_ethernet_0.inst.eth_buf.U0.TX_INTFCE_I.TX_MEM_INTERFACE.TXC_MEM.xpm_memory_base_inst.config_drc File: /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 492
Simulation running at time 5000ns
Simulation running at time 10000ns
Simulation running at time 15000ns
Simulation running at time 20000ns
Simulation running at time 25000ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Configured DUT with control word 69 at time 100620ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Simulation running at time 105000ns
Simulation running at time 185000ns
Simulation running at time 265000ns
Simulation running at time 345000ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Configured DUT with control word 61 at time 354215ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Simulation running at time 425000ns
Simulation running at time 505000ns
Rx Stimulus: 555215ns sending 5 frames at 1G ...
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
FRAME DROPPED by Address Filter
Simulation running at time 585000ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Configured DUT with control word 62 at time 664983ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Simulation running at time 665000ns
Simulation running at time 745000ns
Simulation running at time 825000ns
Rx Stimulus: sending 5 frames at 100M ...
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
FRAME DROPPED by Address Filter
Simulation running at time 905000ns
Simulation running at time 1005000ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Configured DUT with control word 63 at time 1024098ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Rx Stimulus: sending 5 frames at 10M ...
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
Simulation running at time 1505000ns
** Note: Comparing Transmitted Frame with Injected Frame
FRAME DROPPED by Address Filter
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Configured DUT with control word 61 at time 1620978ns
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
Rx Stimulus: 1822006ns sending 5 frames at 1G ...
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
** Note: Comparing Transmitted Frame with Injected Frame
FRAME DROPPED by Address Filter
Test completed successfully
Simulation Stopped
$stop called at time : 1826147487 ps : File "/group/xircss/nanz/Forums/axienet/axi_ethernet_0_ex/imports/axi_ethernet_0_demo_tb.v" Line 1243
run: Time (s): cpu = 00:00:31 ; elapsed = 00:01:40 . Memory (MB): peak = 9114.184 ; gain = 0.000 ; free physical = 51245 ; free virtual = 261715

 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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d93
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Registered: ‎06-25-2021

Since it is working for you @nanz I have searched a little harder. It is indeed working if the simulator target language is set to "Mixed". In my project I had the target language set
to "Verilog" and opened the example design of the AXI Ethernet Subsystem from my block design. The generated example design inherited the "Verilog" target language which
lead to an unworking simulation but I can not comprehend why. At least now the subsystem is functional again.



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nanz
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Registered: ‎08-25-2009

Hi @d93 ,

Thanks for your findings. I will test and file a Change Request if needed. I will update. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
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nanz
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Registered: ‎08-25-2009

Hi @d93 ,

I have reproduced the issue and then I went ahead to file a Change request regarding the issue. Thank you!


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
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nanz
Moderator
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376 Views
Registered: ‎08-25-2009

Hi @d93 ,

I've got an update that - Main wrapper for axi ethernet is in verilog but certain subcores such as axi ethernet buffer, binary counter and shift ram are generated in VHDL irrespective of language. In addition this encrypted rtl (<core>_rfs) is in vhdl for most subcores. So its not possible to run simulation with language set to verilog.

Hope this answers.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

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d93
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Registered: ‎06-25-2021

Alright, that clears it up. Thanks @nanz.

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