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ashivers
Visitor
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Registered: ‎04-08-2021

AXI Ethernet Lite TX Buffer not available

Hello,

I am trying to use the AXI ethernet lite module on a custom HW solution. However, when I attempt to init the EMAC in software, the call to XEmacLite_TxBufferAvailable always returns false. Digging into the call, both the TxPingBusy and TxPongBusy calls are showing that XEL_TSR_XMIT_ACTIVE_MASK is set and the XEL_TSR_XMIT_BUSY_MASK is not set, so it means the buffer is showing as active, but busy for some reason. 

/*
   * Initialize the EmacLite device.
   */
  ConfigPtr = XEmacLite_LookupConfig(XPAR_AXI_ETHERNETLITE_0_DEVICE_ID);
  if (ConfigPtr == NULL) {
    return RET_GENERAL_ERROR;
  }
  ConfigPtr->Loopback = 0;
  Status = XEmacLite_CfgInitialize(&axi_ethernetlite_0_EmacLite, ConfigPtr, ConfigPtr->BaseAddress);
  if (Status != XST_SUCCESS) {
    return RET_GENERAL_ERROR;
  }

  /*
   * Set the MAC address.
   */
  XEmacLite_SetMacAddress(&axi_ethernetlite_0_EmacLite, ee_eth_addr);

  /*
   * Empty any existing receive frames.
   */
  XEmacLite_FlushReceive(&axi_ethernetlite_0_EmacLite);

  /*
   * Check if there is a Tx buffer available, if there isn't it is an
   * error.
   */
  if (XEmacLite_TxBufferAvailable(&axi_ethernetlite_0_EmacLite) != TRUE) {
    return RET_GENERAL_ERROR;
  }

As you can see, my code is pretty basic, so I am unsure as to why the EMAC won't start up correctly... Does anyone have any advice?

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9 Replies
nanz
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478 Views
Registered: ‎08-25-2009

Hi @ashivers ,

I suggest to take a look at Xilinx's emaclite driver first and see if you missed any init steps. Here is the wiki page and you can find the drivers on github. 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842430/Emaclite+Standalone+Driver

 


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ashivers
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Registered: ‎04-08-2021

Hi @nanz,

I used that guide as my starting point, specifically the xemaclite_polled_example.c. I set my device up the same way as it is shown in the example, except I disable loopback and call the flush RX before I check the status of the TX buffer. Neither of those should have an effect on the TX buffer, but I tried commenting those sections out to make it as close as possible to the example, and the same issue persists. Are there any blockDesign examples that go along with the C file examples, maybe I am missing something in my configuration of the device... but I cannot imagine what since there really aren't that many options? I attached some screenshots anyway.bd_screenshot.pngconfig_screenshot.png

As you can see in the first screenshot I disconnected the MII output of the EMAC lite to see if maybe something it was connected to was causing the issue and try to isolate the module, but it did not help. The issue occurred when it was connected and disconnected regardless. 

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nanz
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468 Views
Registered: ‎08-25-2009

Hi @ashivers ,

Xilinx does not have an up-to-date example. But some forum customers did this, for example:

https://forums.xilinx.com/t5/Ethernet/AXI-EthernetLite-gt-Vitis-errors-with-lwIP-quot-Failed-to-create/td-p/1217103

There is a block design to refer to, xci file of the core and xsa file too. Maybe you could compare this customer's design to yours and see the differences. 


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ashivers
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Registered: ‎04-08-2021

@nanz,

I don't see any obvious difference, but I'll keep digging. Would you happen to know if there is any reason the TX Buffer would signal as busy if the MII output of the driver isn't connected? Just want to check if that's a valid scheme for the time being or if I have to change it as I'm testing stuff out. Going to look through the docs again as well.

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ashivers
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Registered: ‎04-08-2021

@nanz ,

I've been working on it some more this morning and yesterday, and still haven't gotten anywhere. I connected it up just a EMAC, and enabled internal loopback mode to try and get just it isolated. I've also added in the self test code from https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/emaclite/examples/xemaclite_selftest_example.c since it seems to be the simplest way to see if the EMAC is instantiated correctly, however it fails every time, specifically in the code section:

/*
	 * Write the TestString to the TX buffer in EMAC Lite then
	 * back from the EMAC Lite and verify
	 */
	XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
			       sizeof(TestString));
	XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
			      sizeof(ReturnString));

	for (Index = 0; Index < 4; Index++) {

		if (ReturnString[Index] != TestString[Index]) {
			return XST_FAILURE;
		}

		/*
		 * Zero the return string for the next test
		 */
		ReturnString[Index] = 0;
	}

of XEmacLite_SelfTest(). Which isn't really that surprising since that is testing the TX buffer.

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dgisselq
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Registered: ‎05-21-2015

@ashivers ,

Do be aware that there are several AXI bugs found in the AXI ethernet lite core.  These have been reported to, and acknowledged by Xilinx yet neither fixed nor errata written for them.  You might need to check if the area optimized interconnect works (which won't trigger the bugs to my knowledge) vs the performance optimized interconnect.  These bugs include the AXI ethernet lite core locking up on read returns, and/or writing data to the wrong address.

Dan

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ashivers
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Registered: ‎04-08-2021

@dgisselq ,

Well thats... fun. I apologize I'm relatively new to xilinx, I worked with Altera stuff a few years ago, but this is my first time with Vivado tools. Looking at the interconnect, its currently set to "Custom" optimization. I'm not sure where that "Custom" is specified yet. Would you suggest trying size or performance optimization? Looking at that article it looks like the lock-up they are talking about is specifically related to writing and reading in the same clock cycle, which I'm not even getting to the point of trying to write yet haha. Either way, thanks for the heads up.

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dgisselq
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Registered: ‎05-21-2015

@ashivers ,

That's just one of the lockups.  The other lockup is associated with not setting RREADY before RVALID.  The Xilinx core will wait for RREADY before it sets RVALID, in violation of the AXI spec.  I think the area optimized interconnect will set RREADY as soon as it sets ARVALID and then hold it high until RLAST, but the performance optimized interconnect can't do that.  The performance optimized interconnect has to arbitrate answers among possibly several read returns, so may need to hold RREADY low until a particular design has won arbitration.

Dan

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ashivers
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Registered: ‎04-08-2021

@dgisselq Re-generated with the interconnect set to size optimized, no change. I am going to try to do a blank project with just the EMAC in it, maybe some other item is breaking it in my current project, but I can't figure out what.

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