cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
csommer
Observer
Observer
356 Views
Registered: ‎02-03-2021

AXI Ethernet SGMII 125MHz differential clock input

Jump to solution

Hi,

I am integrating the AXI 1G/2.5G Ethernet IP on a Zynq 7020 living on a custom-made board to interact with an external Marvell 88E1512 PHY over SGMII.
The 1G/2.5G Ethernet PCS/PMA IP included in the core of the AXI Ethernet IP requires a 125 MHz differential clock.

The 88E1512 has a 125 MHz single ended clock output synchronized with its 25 MHz reference clock.
Do I need to use that 125 MHz output from the PHY for the Ethernet IP in the Zynq to work properly?
Or is it okay to use another external differential crystal oscillator that is not sync'd with the PHY?

0 Kudos
1 Solution

Accepted Solutions
nanz
Moderator
Moderator
308 Views
Registered: ‎08-25-2009

Hi @csommer ,

It's ok to use an external differential crystal oscillator for the IP. 

I would recommend to look at PG047 for clocking details:

https://www.xilinx.com/support/documentation/ip_documentation/gig_eth_pcs_pma/v13_0/pg047-gig-eth-pcs-pma.pdf

nanz_0-1612431488278.png

 

nanz_1-1612431508072.png

 

 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

2 Replies
nanz
Moderator
Moderator
309 Views
Registered: ‎08-25-2009

Hi @csommer ,

It's ok to use an external differential crystal oscillator for the IP. 

I would recommend to look at PG047 for clocking details:

https://www.xilinx.com/support/documentation/ip_documentation/gig_eth_pcs_pma/v13_0/pg047-gig-eth-pcs-pma.pdf

nanz_0-1612431488278.png

 

nanz_1-1612431508072.png

 

 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

csommer
Observer
Observer
266 Views
Registered: ‎02-03-2021

Hi @nanz,

Thanks a lot for your quick reply, it's clear now.
I don't see an easy way to use the single ended clock output of the PHY with the differential clock input of the IP.
So my best bet here is to use Figure 6-1 implementation you shared from PG047.

0 Kudos