AXI stream interface in 40G Ethernet subsystem (zynq ultrascale device)
I am working on 40G/50G Ethernet subsystem example design. In the same design , there is exchange of data between core(I_ethernet_0_top.v) and packet generator module (I_ethernet_0_pkt_gen.v) according to AXI4 protocol. So, there must be axi master and slave interface in core and packet generator respectively, vice-versa. But I am unable to find axi master and slave interface.