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nishihara
Observer
Observer
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Registered: ‎10-01-2018

About SGMII Operation with AXI 1G/2.5G Ethernet Subsystem

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Hello

I want to use the AXI 1G/2.5G Ethernet Subsystem for UDP communication.
We ran a simulation and found that SGMII in TX data
It doesn't change.
I was checking the difference between the ethernet subsystem demo data and the ethernet subsystem demo data, but it seems to be working up to gmii_txd being input to the internal PCS.
From there, what is happening during the conversion to sgmii?

 

 

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cap_demo.PNG
cap_sim.PNG
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nishihara
Observer
Observer
428 Views
Registered: ‎10-01-2018
Thanks for the answer.

Self-resolved.
I made a mistake in setting the access register to MDIO, and I was able to confirm that txdata transitions to something other than IDLE by returning it successfully.

Sorry for the simple mistake.

View solution in original post

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nanz
Moderator
Moderator
504 Views
Registered: ‎08-25-2009

Hi @nishihara ,

I am not sure if I understand what your exact questions are.

Do you ask about SGMII simulation that does not work or how SGMII works in general? Please be more specific on your questions. What is your expectation in simulation?


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guozhenp
Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎05-01-2013

The 1st screenshot has the packet data on "txdata[7:0]" while the 2nd one only has IDLE (BC50) on "txdata[7:0]"?

Is this the question?

Does SGMII get link up first, e.g. checking SGMII "status_vector"?

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nishihara
Observer
Observer
448 Views
Registered: ‎10-01-2018

I am running a simulation with TX output connected to RX. status_vector changes from x020b to x0203. (This is equivalent to the demo simulation).

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nishihara
Observer
Observer
439 Views
Registered: ‎10-01-2018
Sorry for the vague question.

We are checking the operation through simulation, but there is no change in the output from the IP, so I am asking this question.


When I input data into the TX port of the Ethernet subsystem, the output is a fixed value (IDLE?).
The first screenshot is a sample simulation result and the second is the actual simulation result of running it.
We analyzed the internals and it seems to be working up to GMII, but
sgmii does not seem to be working. Is there any cause?

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guozhenp
Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎05-01-2013

Need to see all the inputs, outputs signals of the SGMII IP core, e.g. configuration_vector, signal_detect ... 

You can also compare them against those in the example design.

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nishihara
Observer
Observer
429 Views
Registered: ‎10-01-2018
Thanks for the answer.

Self-resolved.
I made a mistake in setting the access register to MDIO, and I was able to confirm that txdata transitions to something other than IDLE by returning it successfully.

Sorry for the simple mistake.

View solution in original post

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