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Anonymous
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Aurora 8B10B v5.3 Doubts and issues

Hello

 

I am designing an NoC for which I am planing to use Aurora for inter chip serial communication. I have a few doubts and issue that I am facing. Seeking help from the community. Thanks in advance.

 

So now the doubts that I have are

1. Will two Aurora cores exchanging data work if the clock's are different?

2. To use the core with my  application what are the minimum modification that I should make. To my understanding only the farme generator module and frame check module needs to be replaced with my application. what else needs to be understood?

 

The issues that I am facing are:

 

1. I generated the core using Corgen of Aurora 8B10B v5.3 for Virtex V device. which generated the core with example design and a test bench. This test bench instantiates 2 aurora cores which are exchanging data. now I made a slight modification in the design in the clock period such that the two instantiated core are working a different clocks. But the results obtained are not as expected. Please find the screen shot below.

 

in the example test bench the modification i made is shown below

 

 

module EXAMPLE_TB;

//*************************Parameter Declarations**************************

parameter SIM_MAX_TIME = 525000; //To quit the simulation
//156.25MHz GTP Reference clock
parameter CLOCKPERIOD_1 = 6.4;
parameter CLOCKPERIOD_2 = 12.8; ---------------  modified... before modification the peroid was 6.4.

 

 

The signal channel_up is never asserted in this case that means there is no data transfer. 

 

How to correctly modify the design so make the core work at different clock frequency??

 

 

Thanks and regards

 

Saurabh Agrawal

Indian Institute of Technology Bombay

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1 Reply
venkata
Moderator
Moderator
8,390 Views
Registered: ‎02-16-2010

First, you are using Ubuntu OS. This is not supported OS.

Second, Aurora testbench instantiates two aurora cores of same configuration. If you change the REFCLK period, the effective line rate will change.

If you need to simulate two aurora cores with different clock frequencies, generate them seperately with all the core options to be same except the REFCLK frequency. Customize the test bench of one of the example design to suit your requirement.

Yes. It is only required to replace frame generator and frame checker to use the Aurora core for your application.

While you do this, make sure you follow the required guidelines for the data transfer as mentioned in the core user guide.
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