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9,321 Views
Registered: ‎11-04-2010

Aurora Core on ML605 evaluation boards

I am using two ML605 boards to verify GTX connection at X0Y18. First, I test IBERT core on these boards. It works fine when the cable loop back to the same board. When connecting board to board, it has about 2% error rate and link drop frequently. Xilinx FAE tested the boards and concluded the board has defects and replaced them with two working boards. These two new boards work fine with IBERT core. However, when I tested Aurora core which uses same location X0Y18, 1 -lane duplex channel, the similar symptom happened again. It works perfect when cable loop back to the same boards. When connecting board to board, "channel up", "lane up" and "hard error" are toggling. "tx_lock_i_i" is asserted and "pll_not_locked_i" is deasserted. The problem looks to me is more like hardware defect. Do you have any idea what's wrong? Is there any way to work around the problem? 

Chipscope with Aurora core.bmp
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10 Replies
Xilinx Employee
Xilinx Employee
9,317 Views
Registered: ‎01-03-2008

Re: Aurora Core on ML605 evaluation boards

When you ran the IBERT tests between the two boards, did you determine the best settings for the TX output swing, pre-emphasis and RX equalizer?

 

These values should be used with the GTX blocks that make up the Aurora core for optimal results.

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9,264 Views
Registered: ‎11-04-2010

Re: Aurora Core on ML605 evaluation boards

Hi,

    I tried the other way around. I copied Aurora settings to IBERT. IBERT link is always stable. The settings I changed are in the following sections.

TX Driver and OOB signaling

RX Decision Feedback Equalizer

RX Driver,OOB signalling,Coupling and Eq.,CDR

 

The only thing made big different is TXDRIVE_LOOPBACK_HIZ and TXDRIVE_LOOPBACK_PD in "TX Driver and OOB Signalling" section. In Aurora core, these two attributes are "FALSE", but it is "TRUE" in IBERT. If the settings change to "FALSE" in IBERT, the link losses right away. However, if I put "TRUE" in Aurora core, the "channel_up" and "lane_up"  never assert. I can't find any definition of these two attributes in "V6 GTX Receiver User Guide". Are these two attributes the problem? Besides these two attributes, I can't find any settings difference for the TX output swing, pre-emphasis and RX equalizer.

  

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Xilinx Employee
Xilinx Employee
9,240 Views
Registered: ‎01-03-2008

Re: Aurora Core on ML605 evaluation boards

First check the length of the SMA cables, lay them flat and make sure that they are the same

 

If the RX AC coupling is on then turn it off (I know that IBERT does it too, but this is only for PCIe)

      AC_CAP_DIS = TRUE

 

 RX Termination should be set correctly

      RCV_TERM_GND = FALSE

      RCV_TERM_VTTRX = TRUE

 

How is the MGT REFCLK generated for your design on both boards?

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Xilinx Employee
Xilinx Employee
9,228 Views
Registered: ‎04-06-2010

Re: Aurora Core on ML605 evaluation boards

I was wondering if you're using the example design from the Aurora core?  The reason I ask is because there's a bug in the example design where the clock correction module is held in reset once lane_up is asserted.  This prevents clock correction sequences from being transmitted to eachother.  This means that if your refclks are not synchronous, then you're going to have issues eventually.

 

Open the top level example design module (mine is called "aurora_8b10b_v5_2_example_design") and invert the "lane_up_reduce_i" signal before it goes into the clock correction module.  

 

Hope this helps...

 

9,195 Views
Registered: ‎11-04-2010

Re: Aurora Core on ML605 evaluation boards

I am using example design. I tried your suggestion and it works!! Thank you very much for your help.

 

 

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Teacher eteam00
Teacher
9,193 Views
Registered: ‎07-21-2009

Re: Aurora Core on ML605 evaluation boards

I was wondering if you're using the example design from the Aurora core?  The reason I ask is because there's a bug in the example design

Luis, is this bug going to be corrected, or at least documented with a warning and a fix?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Xilinx Employee
Xilinx Employee
9,175 Views
Registered: ‎04-06-2010

Re: Aurora Core on ML605 evaluation boards

I put in the request to fix this last week. This will get fixed, but I'm not sure when.
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Xilinx Employee
Xilinx Employee
9,120 Views
Registered: ‎12-02-2009

Re: Aurora Core on ML605 evaluation boards

This issue will be fixed in ISE 13.1 release

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Visitor zbakerunm
Visitor
8,310 Views
Registered: ‎08-31-2011

Re: Aurora Core on ML605 evaluation boards

It is crazy that this isn't mentioned in the Coregen system.   ISE loves to call home when things go wrong, it seems like coregen could phone home and pop up a little message that says, "hey, this core you just generated is totally bogus.  You should read this forum post <link>"

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Visitor sydundar
Visitor
2,804 Views
Registered: ‎07-17-2012

Re: Aurora Core on ML605 evaluation boards

I have been trying to implement Fiber Interface Using  Aurora Core on ML605 , There is two different versions of  Aurora Core and i have tried both of them. I am using Example_Design of Aurora Core But Channel_Up signal is toggles in every 90us (aproximately) I dont know what is the reason of this problem. 

 

I add exactly same vhd codes of Example_Design of Aurora Core but it doesnt work. Anyone could help me about this issue.

Why Original  Aurora Core for ML605 is not working??

 

(I have genareted for spartan6 board and tested , it works succesfully but no success for ML605 )

 

 

Best Regards.

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