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Observer samer.sabbah
Observer
10,870 Views
Registered: ‎05-03-2008

Aurora Link Problems

I am using Aurora to link two FPGAs together. One FPGA is a virtex5 while the other is a virtex 2 Pro. The Aurora version on the virtex5 is 5.1 while on the virtex 2 Pro is an older version. The Auroa is being used at 2Gbps with a 100MHz clock on both sides.

 

A soft error followed by a hard error is occuring very often on the link. Debugging of the signals showed that the signal RX_NOT_IN_TABLE is getting high just prior to the errors. Sometimes there is a disparity error as well. Before the error occurs there is a series of wrong received data (Zeroes).

 

Could anyone give me some hints to the cause of these kind of errors?

Could the different versions of the Aurora core or different FPGAs be a problem?

 

Thanks

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12 Replies
Xilinx Employee
Xilinx Employee
10,868 Views
Registered: ‎08-10-2007

Re: Aurora Link Problems

Something that is often overlooked is that a link between MGTs in different FPGA families, in this case Virtex-II Pro and Virtex-5, have to be AC coupled.

 

Check the core in loopback on both sides, so V2 Pro back to V2pro and V5 back to V5.

 

Do the LANE_UP and CHANNEL_UP get asserted at times?

 

There should be no problem with linking different version or different families.

Observer samer.sabbah
Observer
10,848 Views
Registered: ‎05-03-2008

Re: Aurora Link Problems

Thanks for the reply

 

There is one difficulty in the situation. I am not developing the  V2PRO... It belongs to a device that we bought and we have to connect to. So loopback can only be done in the V5. This works well... Its also not possible to see what the V2PRO is receiving.. I know what it is sending .. mainly the V5 is receiving the correct data util the error starts to occur... It then gets zeros and then the link breaks ... it takes few clock cycles to reconnect.

 

The lines are already AC coupled .. the LANE_UP and CHANNEL_UP are getting asserted normally

 

Did you mean Loopback from the "far end" of the link?

 

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Xilinx Employee
Xilinx Employee
10,841 Views
Registered: ‎12-02-2009

Re: Aurora Link Problems

What version of the Aurora are you using for V2pro?. You may want to review the GT attributes and update.

 

Btw, Xilinx released Aurora 8B10B v5.2 core last week which has all updated GT attributes.

 

Tuning the GT attributes with lastest and/or recommended values *might* get rid of the soft error issue.

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Observer samer.sabbah
Observer
10,676 Views
Registered: ‎05-03-2008

Re: Aurora Link Problems

I have been trying different methods to solve the soft error problems. Changing the cables, connectors ... ect. without success. The link is initializing .. and i can even send and receive data ... but sometimes soft errors and hard errors are happening.

 

I had a look at the debugging signals. before the error is happening the "RX_NOT_IN_TABLE" is getting asserted. In the attachment there is screen shot from chipscope. What could be the reason for this error?

 

Thanks

AuroraError.JPG
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Visitor naika
Visitor
10,537 Views
Registered: ‎01-11-2010

Re: Aurora Link Problems

Hi,

  I'm also facing similar problem. But the Aurora link is between V4 and V5. It is streaming mode duplex core. sometimes I'm getting a lot of soft errors in V5 when V4 aurora is transmitting and V5 aurora is receiving... could you find any solution?

 

cheers

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Visitor naika
Visitor
10,534 Views
Registered: ‎01-11-2010

Re: Aurora Link Problems

Hi Killi,

  what do you mean by tuning GT attribute.. could you elaborate a bit?

 

cheers

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Observer samer.sabbah
Observer
9,956 Views
Registered: ‎05-03-2008

Re: Aurora Link Problems

Hi .. Were you able to solve the problem with the rocketio? Can you please update us..

 

Regards

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Explorer
Explorer
9,941 Views
Registered: ‎08-12-2007

Re: Aurora Link Problems

Did you check the oscillator? Make sure it's in the range.

As I remember, it's 100ppm total for two link partners.

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Visitor rneufeld
Visitor
8,582 Views
Registered: ‎06-24-2009

Re: Aurora Link Problems

Hi,  I am having the same problem connecting a version 5.3 Aurora core on a Virtex 5 to a version 2 core on a Virtex 2Pro.  Lane Up and Channel Up both get asserted and I can send data but with periodic hard errors that cause dropped frames. Has anyone been able solve this???

 

Tags (1)
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Scholar samcossais
Scholar
4,208 Views
Registered: ‎12-07-2009

Re: Aurora Link Problems


@kka wrote:

What version of the Aurora are you using for V2pro?. You may want to review the GT attributes and update.

 

Btw, Xilinx released Aurora 8B10B v5.2 core last week which has all updated GT attributes.

 

Tuning the GT attributes with lastest and/or recommended values *might* get rid of the soft error issue.


Yes, replacing the GT wrapper with the one generated with transceiver wizard IP in Aurora preset solved the problem in my case (if I remember correctly). I use the Aurora core v5.3 between two Virtex-6.

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Scholar samcossais
Scholar
4,206 Views
Registered: ‎12-07-2009

Re: Aurora Link Problems

By the way, I have a suggestion about that.

 

Wouldn't it be a good idea to make the Aurora IP compatible with the Transceiver wizard wrapper ? It would be much easier to replace the "old" Aurora core GT wrapper with the more frequently updated transceiver wizard.

 

Actually, I have been using Aurora, SRIO and PCIe Xilinx IPs since Virtex-2 Pro, and in my humble opinion I think it would be very convenient for users and also easier for Xilinx to maintain if all your IPs using GTs were able to connect without any modification to the GT wrapper generated with the transceiver wizard (provided the wizard is set with the appropriate preset).

 

In this forum as well as in the Aurora user guide, we are told to preferably use the updated Transceiver wizard GT wrapper instead of the original old one, but to be honest it is quite easy to make a mistake because the ports are totally different between them and there are a lot of ports/parameters ! It took me a lot of time to replace the wrapper, safely checking all the connections/parameters one by one and double check. And then it again took me some more time to verify everything in simulation / hardware because the replacement was pretty much as if I partially recoded the Aurora IP.

 

In addition, users are able to more easily tune the GT settings by using the transceiver wizard IP.

Visitor lakata
Visitor
3,686 Views
Registered: ‎05-08-2014

Re: Aurora Link Problems

I don't understand how Xilinx gets away with this.

 

Xilinx recommends rerunning the GTH wizard to generate a new wrapper file that is totally incompatible with the file it is supposed to replace. 

 

I just ran GTH wizard (3.1) and the wrapper file has an entirely different port format than the wrapper generate by Aurora wizard (10.1). Both of these wizards are from the 2013.4 Vivado package.  Ports are renamed and the entire port list is in a different order.

 

I *could* understand if 1 or 2 lines were incompatible and needed a *little* tweak, if you used different Vivado releases. But  this is the SAME VIVADO release.  There's no excuse.


What's going on here? How can these 2 wizards be so out of sync?