05-29-2015 08:36 AM
We are planning to make a "ring" topology with 3 Zynq 706 boards connected with their SMA connectors. We are considering the Aurora 64B/66B PHY. I have been through the XAPP1216, and XAPP1192 application notes, and have a few questions. I hope they do not sound "funny" as I am new to the board-to-board connectivity field:
1. Is the external differential clock mandatory? According to XAPP1216, the two KC705s do not use an external clock. In contrast, when a KC705 is connected to a Zynq706, an external differential clock is provided to both boards.
2. Within each Zynq, we would like to utilze the ARM cores, so again according to XAPP1216, we should make the following connections: ARM <-> AXI interconnect <-> Chip2Chip <-> Aurora. My question is that if the Chip2Chip works only at a master-slave apporach. Can all nodes be equal (e.g. masters), since otherwise I think a ring topology would not work.
Any feedback would be great!
06-01-2015 04:31 AM
11-18-2015 10:18 AM
11-21-2015 09:11 AM
I need help for implementing small application - receiving data from Ethernet and transmitting data through gtx(aurora). I am using zc706 board. I am using Block Design to implement this.
In my block design, I am using axi interconnect<->axis chip2chip(master)<->aurora6466b(streaming)<->axis chip2chip(slave)->axis interconnect.
I am using lwip application and modifying.
To writing data and reading data to ddr3(PS),Wr_word,rd_word and memcpy APIs are used.
My problem is:
How can we send Data(Read from ddr3) to aurora(S_AXI_TDATA)?
how can we receive Data(received from aurora(M_AXI_TDATA)?
I need some references for coding in SDK
I tried with AXI DMA but it gave errors in clocking part.
How can we overcome this?
How can we take data from block design (dma or axi interconnect or chip2chip ip)to topmodule which is in vhdl?
Any body .........
10-07-2016 04:28 PM
Many replies say "Don't use a fabric generated clock; instead use an external reference clock" for Aurora in the ZC706.
I understand that the fabric clock is perhaps not good enough for board to board communication.
However, it seems strange that all of the manuals and replies and pictures show people using an external clock generator to supply a 156.25 MHz clock when using the ZC706 board, when there is apparently already a perfectly good one supplied on the board.
The ZC706 has an on board 156.25 MHz clock, supplied by the Silicon Labs Si570BAB0000544DG, known as U37
in the schematic. This clock defaults to 156.250 MHz, which is one of the reference clock frequencies that the GTX
is designed to use. It is described as a a low-jitter (50 ppm) 3.3v LVDS differential oscillator, and is brought in to pins AF14 and AG14 of the XC7Z045. It can be run at frequencies between 10 MHz and 810 MHz.
Can we connect this clock as the reference clock for the GTX Quad bank 111?
I have been trying this myself, and I am in a maze of twisty error messages, none helpful.
It would be most excellent if there was a reference design for this!
10-10-2016 04:16 PM
There is a JESD204 reference design that includes sample code for interfacing to the Si570 programmable oscillator and Si5324 jitter attenuator on the ZC706 board. The clock from the Si5324 is suitable for use as the GTX transceiver's reference clock.
The link to the reference design is shown in the solution to the following post: