03-05-2014 03:27 PM
Hi,
I am trying to implement an Aurora link between the two transceivers in the X0Y3 tile of the ML507 (XC5VFX70T) board. I am trying to complete a loopback test over a SATA link. How many Aurora cores would I need to generate? My understanding is that each Aurora lane/channel uses one transceiver so I would be needing two separate Aurora cores. I am not sure how i would combine them in a single project. Any help is appreciated.
03-14-2014 10:50 AM
03-05-2014 08:58 PM
03-05-2014 11:12 PM
The following AR http://www.xilinx.com/support/answers/21263.htm also having useful knowledge related to your query
03-06-2014 09:41 AM
03-07-2014 03:07 PM
The issue here is that both transceivers are in the same tile so i can't just generate a core with 2 lanes.
03-10-2014 08:39 PM
03-13-2014 01:39 PM
I have looked into that portion of the UG but I am not sure about how to implement the stiching of the two cores in one project. Do i have to re-label signals of the individual cores on the top level and connect them at that level? Any previous work that i can take pointers from?
03-14-2014 10:50 AM
05-21-2014 03:33 AM
05-21-2014 05:04 AM
05-21-2014 09:44 AM
Hi,
My problem is wtih GTX & SATA . Anyways give me thread of PCIE
Thanks
05-21-2014 10:43 PM