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Visitor tarakesava
Visitor
8,462 Views
Registered: ‎05-21-2014

Aurora simplex Lane up failed in spartan 6 FPGA based board.

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We are using Aurora simplex timer based streaming mode in our design.Aurora simplex-TX of one board is connected to Aurora simplex-RX of other board.We generated Aurora Simplex-TX and Aurora Simplex-RX core from core generator (Auora8b/10B V8.3) and generated bit files with examples design.

 

we programmed bit and started testing,observed that aurora RX-Laneup is not at all coming up.

 

After that we generated bit files with aurora duplex to check connectivity between boards,its working fine.But with simplex bit files ,we are not seeing any lane up and also didnt find any alignement sequence( i.e BC4A 4A4A BC4A4A).But we are seeing lane intialization( i.e BC4A 4A4A BC4A4A) pattern at the transmitter side.

 

Note:-

1)we  are using defualt timers at transmitter side (C_ALIGNED time 6143 and C_VERFIED timer 8191)

2)Simplex Transmitter used  in LX45T board and Simplex Reciever used in LX25T board.

3)GTP reference clock = 100MHz, lane speed = 1.25 Gbps

4)we are using ISE 14.5 version.

 

Please find the attached TX and EX project files.

 

Thanks

Tarak

 

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1 Solution

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Moderator
Moderator
13,214 Views
Registered: ‎02-16-2010

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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By pma_init, I was referring to GT_RESET_IN signal. Please try the suggestion about asserting GT_RESET_IN at Simplex Rx, followed by RESET (not GT_RESET) input at Simplex Tx
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Moderator
Moderator
8,445 Views
Registered: ‎02-16-2010

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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Are you sure the connectivity between Tx and Rx is correct in case of Simplex link?

What is the status of resetdone, rxbyteisaligned signals at the Simplex Rx?

Can you try asserting pma_init at the Rx, followed by RESET (not GT_RESET) input at Simplex Tx?
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Visitor tarakesava
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8,405 Views
Registered: ‎05-21-2014

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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Dear Venkata,

 

sorry for late reply,these are the comments for your questions

 

Q1)Are you sure the connectivity between Tx and Rx is correct in case of Simplex link?

 Ans)yes,Its correct.we tested using full duplex and same we reatained for testing simplex too.

 

Q2)What is the status of resetdone, rxbyteisaligned signals at the Simplex Rx?

Ans) resetdone is  high.Regarding rxbyteisaligned ,most of times its zero and sometimes its going High.

 

Q3) Can you try asserting pma_init at the Rx, followed by RESET (not GT_RESET) input at Simplex Tx?

Ans)We are not finding any  pma_init signal ,please let me know which module we can find it.

 

We have done same simplex testing in virtex-5 based boards.Below are the our observations.

  • Simplex tx and RX generated from Aurora 8b/10b V5.2.
  • Bit files are generated with example design and  deafault parameters using  ISE 13.3
  • We observed lane up is coming both sides ,but rx losing link with in sometime.
  • After observing the watchdog timer signals at RX side and found that  Initialization timers at transmitter side is more.
  • After fine tuning timers,RX link is got stabilized  and started working at align timer = 1310 and verify timer = 1700.
  • After this we changed the timers and other paramaters for spartan-6 based board same as Virtex-5  based board.  
  • Made similar setup,Same optical module and same cable length.
  • We didnt find any link  up at rx side and also and didnt find any Initialization sequence.we are always seeing some wrong data at RX side.
  • Due to this simplex RX side is not get Initializied during link training.

Please suggest and let us know any parameters need to change for spartan-6 FPGA's.

 

Thanks

Tarak

 

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Moderator
Moderator
13,215 Views
Registered: ‎02-16-2010

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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By pma_init, I was referring to GT_RESET_IN signal. Please try the suggestion about asserting GT_RESET_IN at Simplex Rx, followed by RESET (not GT_RESET) input at Simplex Tx
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Visitor tarakesava
Visitor
8,383 Views
Registered: ‎05-21-2014

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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Thanks Venkata,

 

We done according to  your suggestion.,After this  we saw lane up at receiver side ,but after sometime lane up is deasserting.These are the our observations

  • We observed bucket_full_r signal is going high in chipscope pro,Due to this reset is asserting at reciever side and lane up is deaserting.
  • To confirm the the above condition ,we commented bucket_full_r signal ,generated bit file and tested same.
  • Now link is stable.
  • Please suggest  how come we can comeout from this problem.
  • We observed one more thing,Once lane is got stabled rxbyteisaligned is going low and coming back high.
  • But link is stable.Please let us know ,is that fine?

Thanks

Tarak

 

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Visitor shanekong
Visitor
8,367 Views
Registered: ‎04-08-2014

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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 hi tarak,we are doing almost the same work now. 

i am tring to use aurora duplex between two spartan 6 -45t FPGA based board, and encounter a problem that both lane up 

and channel up failed. 

 

then i test self-loop, connecting the TXP/TXN to RXP/RXN on one board, it works well. 

is there any thing ignored in my design? and how could i check the problem? 

 

notes:

aurora duplex    framing  mode/ streaming mode  other parameter are set as default referred to board.

 

 

 

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Visitor tarakesava
Visitor
8,359 Views
Registered: ‎05-21-2014

Re: Aurora simplex Lane up failed in spartan 6 FPGA based board.

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1)If your are using SFP module for communciation between two boards,Please check the what is the status of Tx-Disable and LOS signal of SFP module.Both signals should be zero.

2)I suggest you to check the two board connecvity using IBERT.This help us to know about the harware is fine or not.

 

 

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