07-29-2019 10:43 PM - edited 07-31-2019 01:27 AM
I am trying to use VHDL to control MDIO unit in Axi Ethernet Lite.
While simulating I observe , that while initiating WRITE access the procedure i follow is
1. After filling data in MDIOWR (0x07E8) & MDIOADDR (0x07E4)
2. I trigger MDIO_EN of MDIOCTRL (0x07F0) follwed by setting status bit of MDIOCTRL (0x07F0)
3. Then poll MDIOCTRL (0x07F0) until status bit is '0'
here in I observe that after setting status bit '1' Write Transaction begins. After cetrain clock cycles status bit turns '0', but I could observe phy_mdio_t remaining '0' as in attached image. phy_mdio_t remains so for few more clock cycles and later get deasserted.
Does this not mean that the cycle is not yet complete?? If i read MDIOCTRL (0x07F0) it indicates that MDIO module is ready for a new transaction. Where as it is not??
Here If I trigger one more MDIO access , say READ, after status bit going '0' within this time gap. No MDIO access is initiated. I have to wailt until
phy_mdio_t = '1'
I was expecting that status bit inidcated completion of MDIO access.
Please let me know the prudent mode of use MDIO interface , what delay to apply between MDIO commands etc. so that MDIO transaction are complete in true sense.