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Observer
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Registered: ‎10-01-2019

CMAC 100G underrun issue with 64 byte packet

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I have an axi stream fifo -> axis_switch -> LBUS -> CMAC configuration. I am using the same CMAC and axi stream fifo for rx/tx packets. I have an issue where whenever I send the CMAC a 64 byte packet, the CMAC asserts the tx_unfout signal, indicating an underrun. I verified the data coming out of the fifo, switch, and lbus. I have put ila's on both sides of the LBUS to verify the data going in on the AXI bus and coming out of the lbus into the CMAC, all of the signals look valid. However, if I send anything over 64 bytes, it appears to work just fine, it basically just bumps it up to a 128 byte packet (e.g when sending 65 bytes). Also, on the RX side, I can received 64 byte packets just fine, the issue only occurs on the tx side.

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Observer
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Registered: ‎10-01-2019

I was under the assumption that the axi the lbus converter was a Xilinx IP, instead it came from one of our contractors, it appears the bug is within the converter. I was able to fix the issue and now I am in the process of converting the same project to 2019.1. I am curious how easy it is to implement the 100G CMAC with the built in axi<->lbus converter. What a great learning experience this has been!

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Registered: ‎10-01-2019

I have attached two waveforms, the first one is the 64 byte transaction, and the second is the 128 bytes transaction.

The ila is connected to the axi-to-lbus ip block, with all the output signals from the cmac tx lbus to the CMAC, I also included some other CMAC stats. As shown the cmac_tx_unfout (CMAC tx under run) is being asserted on the 64 byte transaction. I believe the lbus transaction looks valid.

The axi stream data fifo feeding into the lbus has packet mode enabled, to remove any underrun issues on the axi fifo to lbus connection since the CMAC clock is faster than the axi clock.

I just used random data for demonstration purposes and to make debugging easier, but with a well formed Ethernet frame, anything greater than 64 bytes works, verified in wireshark.

Any help is greatly appreciated.

xilinx_fig2.png
xilinx_last_fig.png
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Observer
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Registered: ‎10-01-2019

Upon further investigation, the sop and eop signals must be asserted with the enable signal, however the enable signal is going low before the eop is asserted.

 

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Observer
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Registered: ‎10-01-2019

I was under the assumption that the axi the lbus converter was a Xilinx IP, instead it came from one of our contractors, it appears the bug is within the converter. I was able to fix the issue and now I am in the process of converting the same project to 2019.1. I am curious how easy it is to implement the 100G CMAC with the built in axi<->lbus converter. What a great learning experience this has been!

View solution in original post

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