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Visitor
Visitor
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Registered: ‎04-16-2019

CMAC AXIS interface in Vivado 2019.2 has misaligned data bytes

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I am trying to use the AXIS interface on the CMAC 3.0 using Vivado 2019.2.  Some packets/bursts of packets come through as expected, but others have a misalignment between data byte lanes, for example with a 512-bit tdata bus:

clock 0
  tvalid = 1
  tlast = 0
  tuser = 0
  tkeep = 0xfefffffebffffffe
  tdata = first word - bytes are valid where corresponding tkeep bits = 1

clock 1
  tvalid = 0
  tlast = 0
  tuser = 0
  tkeep = 0x0100000140000001
  tdata = bytes are valid where corresponding tkeep bits = 1  (i.e., the rest of the data from the first word)

clock 2
  tvalid = 1
  tlast = 0
  tuser = 0
  tkeep = 0xfefffffebffffffe (always the same pattern within a packet or within a burst of packets)
  tdata = second word - bytes are valid where corresponding tkeep bits = 1

clock 3
  tvalid = 1
  tlast = 1
  tuser = 0
  tkeep = 0xffffffffffffffff
  tdata = all bytes are valid, but this is a mix of the second word and third word!

clock 4
  tvalid = 0
  tlast = 1     (!)
  tuser = 0
  tkeep = 0x0100000140000001
  tdata = bytes are valid where corresponding tkeep bits = 1  (i.e., the rest of the data from the third word)

This does not seem like a timing problem, in that the tkeep pattern is consistent across a packet/burst of packets, and that some packets do not exhibit this problem.

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Visitor
Visitor
269 Views
Registered: ‎04-16-2019

I was able to solve the issue: I had been using the CMAC's gt_rxusrclk2 output to clock my receive-side logic, and gt_txusrclk2 to clock my transmit-side logic. 

By uing the gt_txusrclk2 to clock my receive logic, the AXI-S bus behaves as expected.

Following the user guide, I feed the gt_txusrclk2 back into the rx_clk input.  The datasheet is not 100% clear on what logic is clocked off of what reference so figured my original rx-rx / tx-tx clocking made sense.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Is the issue in simulation or on board?

Can you reproduce the issue in simulation?

Could you try GT PMA near end loopback first? Does CMAC still have the issue with the data loopbacked?

Could you just upload the screenshots to show the issue?

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Visitor
Visitor
270 Views
Registered: ‎04-16-2019

I was able to solve the issue: I had been using the CMAC's gt_rxusrclk2 output to clock my receive-side logic, and gt_txusrclk2 to clock my transmit-side logic. 

By uing the gt_txusrclk2 to clock my receive logic, the AXI-S bus behaves as expected.

Following the user guide, I feed the gt_txusrclk2 back into the rx_clk input.  The datasheet is not 100% clear on what logic is clocked off of what reference so figured my original rx-rx / tx-tx clocking made sense.

View solution in original post

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