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Observer
Observer
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Registered: ‎09-20-2018

Cannot Create a continuous Data Stream with Aurora 64/66b Core

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I am using two Virtex 7 680T FPGAs with one as the transmitter and the other as the receiver. I notice when simulating the Example Design that the transmitter stops(tready low; data holds) for 16ns every 512ns. This carries over to the receiver as it stops (valid low; data holds) for 80 nsec every 2.56 usec. This is a 2 lane transmission where user_clk is 62.5MHz; refclk is 125MHz; LIne Rate is 4Gbps; init_clk is 94MHz; drp_clk is 125MHz.

It seems that if I use a FIFO on the receive size to write in the 128 bits at 62.5MHz and then hold off for some time before I read out 64 bits at 94MHz, I'll always catch up and the data read will eventually not be continuous as the 80nsec gap will pass through on the read side since the FIFO will be empty.

I've attached a picture of the example simulation. I can see the actual implementation of the two FPGAs work exactly as the simulation shows. Wondering if there are any ways to get a continuous data stream out when using Aurora cores to pass the data between FPGAs.

 

Thanks!

aurora_64b66b_Example_Sim.JPG
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Observer
Observer
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Registered: ‎09-20-2018

Needed to increase to 4 Lanes so that there are 256 bits of data being written into the RX Fifo while 64 bits are read. This covers the overhead and efficiency processing times of the Aurora Cores.

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Scholar
Scholar
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Registered: ‎02-01-2013

Hmm...  512 / 16 = 32 and 64 / (66 - 64) = 32...  I think we're on to something, here...

Are you sure your line rate is 4.000000000 Gbps?  If so, that leaves no time/room for 64/66 coding.

Each line appears to be taking-in 64 bits at 62.5 MHz. That alone is 4.000 Gbps. For 64/66 encoding, the ensuing line rate needs to be (4.000 Gbps * 66/64 =) 4.125 Gbps.

Look at it this way: that's a LOT better than the 5.000 Gbps it would need to be if you were using 8b/10b.

-Joe G.

 

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Observer
Observer
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Registered: ‎09-20-2018

4Gbps is the LIne Rate setting of the Aurora Core using 2 Lanes. The system Line Rate is 6.016Gbps (94MHz @ 64 bits). If my calculations are correct, the Aurora core will operate with a user clk of 62.5MHz @ 128 bits = 8.000Gbps. Should be enough for the overhead of the Aurora Core I would think.

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Observer
Observer
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Registered: ‎09-20-2018

Needed to increase to 4 Lanes so that there are 256 bits of data being written into the RX Fifo while 64 bits are read. This covers the overhead and efficiency processing times of the Aurora Cores.

View solution in original post

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