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Visitor
5,334 Views
Registered: ‎05-20-2010

## Determine latency of GTX links vs Aurora+LVDS

I have a design partitioned over 2 FPGAs. I am trying to determine the benefits of selecting GTX links vs. LVDS to transfer the data between FPGAs.

Target Device  : xc6vlx550t

Target Package : ff1759

Target Speed   : -2

Latency calculations:

1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20 bits input. This means the bits are transmitted at bit-rate = 20*106.25 MHz = 2.125 Gbps.

# of bits to be transferred = 1728

Latency of this interface = 1/(80% of bit-rate * (20/16)*(# of bits transferred/16)) = 1/(2.295+e11) = 4.35+e-12 seconds

2. LVDS+Aurora: The Aurora interface is configured at 600MHz (6 Gbps) with lane width as 2 bytes.

Latency of this interface = 1/(80% of clock rate * (# of bits transferred/16)) = 1/(5.184+e10) = 19.29+e-12 seconds

Is this calculation correct? My assumption for the LVDS calculation is that Aurora does not up-sample the clock frequency by 20 for transmitting data.

Thanks in advance for all the feedback.

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3 Replies
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Scholar
5,328 Views
Registered: ‎02-27-2008

v,

The GT has registers, and fifo's.  These add latency.  Read the user's guides, and look up the latencies.  The Aurora core also has registers, fifo's.  That is more latency.

It will be very hard to beat the LVDS wide parallel path for controllable latency.  The latency pf the wide parallel bus is a clock to send it, and a clock to receive it.  If the clock is 2ns (500 MHz) that in 4ns.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Teacher
5,318 Views
Registered: ‎09-09-2010
This query was also cross-posted to comp.lang.vhdl, see, for instance:
http://www.fpgarelated.com/usenet/fpga/show/98228-1.php
[quote]
Generate both lots of IP.
Write a testbench with both instantiated.
Simulate.
[/quote]

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Newbie
5,252 Views
Registered: ‎09-01-2011

CAn you give us the minimum latency to transfer 64 bit with Aurora, Rapid IO and low level GTX.

Our simulation gives 500 nanos, which is certainly excessive and due to a bad setting.  But I would like to know typical latency figures that we should expect

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