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egrigor
Contributor
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Registered: ‎12-11-2007

Differential Clocks for two instances of Ultrascale+ Integrated 100G Ethernet IP

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Hi,

I'm using a VCU118 board and it has 2 QSFP ports.  I'm associating each QSFP with an instance of Integrated 100G Ethernet hard IP using CAUI-4.

Each integrated core has its own differential gt_ref_clk_p and gt_ref_clk_n inputs which is configured for a 156.25 MHz differential clock source provided by the VCU118 (U38 Si570).

The question I have is:

Is there a way to share the 156.25 MHz clock fed from the first Integrated IP instance into the other instance of the IP, or must there be a separate differential clock source provided for the second Integrated IP instance?

According to PG203, Figure 3-1, there is a 'gt_ref_clk_out' signal fed from the input IBUFDS_GTE3 but I don't see a single-ended gt_ref_clk input for this IP.  Since you can have as many as 9 of these integrated hard IPs in a VU9P FPGA, it seems excessive to require a separate differential clock signals for each instance, so I'm just wondering if there is an option for stitching the same gt_ref_clk to multiple instances of the same IP (of course each instance as its own separate unique GTY and CMAC tile selections).

I know there is a second 156.25 MHz clock source available to me on this VCU118 board (U32/U104) but I'd rather not use this second source if I can just share the first one, routed internal in the FPGA.

 

Thank you

 

 

PG203_Figure3_1.png
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aforencich
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Registered: ‎08-14-2013
I think what you need to do in that case is generate the CMAC core without the transceivers (GTY in example design option), then use the gtwizard to configure the transceivers and clocking the way you need it.

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aforencich
Explorer
Explorer
437 Views
Registered: ‎08-14-2013
I think what you need to do in that case is generate the CMAC core without the transceivers (GTY in example design option), then use the gtwizard to configure the transceivers and clocking the way you need it.

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egrigor
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Registered: ‎12-11-2007

Yes, I think that is what I will need to do.  Right after I posted this question, I found an ealier post on this forum asking a similar question related to the 10G/25G implementation, and the solution suggested there was to implement the GT subcore in the example design rather than having the GT subcore in the core:

https://forums.xilinx.com/t5/Ethernet/Using-a-RefClk-in-multiple-Quads-10G-25G-Ethernet-Subsystem/td-p/1114771

Thank you