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elenp
Newbie
Newbie
991 Views
Registered: ‎05-08-2018

Don't work Aurora 8B/10B core not including shared logic

Hi,

 

I have a question about Aurora 8B/10B.

 

I refer to figure 3-11 of Aurora 8B/10B product guide PG046 and four Aurora are connected on the block design,

only cores with [include Shared Logic in core] enabled will work, and the other three cores will not work.
The operation confirmation was done by using the sample design FRAME_GEN and FARME_CHECK and making it internal loop back.
It is operating normally in simulation.

 

aurora_connection.png

 

 

 

The development environment is as follows.

 

* OS : Ubuntu 16.04 LTS
* Tool : Vivado 2016.2(64bit)
* Device : xc7a50tcsg325-2

 

 

The settings of Aurora are as follows.

 

[Core Options]
* 6Lane Width : 4
* Line Rate : 6.25
* GT Refclk : 156.250
* INIT clk : 59.9994
* DRP clk : 59.9994
* Lanes : 1
* Dataflow Mode : Duplex
* Interface : Framing
* Flow Control : Completion NFC
* Scrambler/Descrambler : OFF
* Little Endian Support : OFF
* CRC : ON
* Additional transceiver control and status ports : OFF
* GT DRP Interface : OFF

 

[GT Selections]
* Lanes : 1
* GT Refclk1 : GTPQ0

 

[Shared Logic]
* include Shared Logic in core : ON(Only one core)
* include Shared Logic in example design : ON(The other three cores)
* Single Ended INIT CLK : ON(Only one core)

 

 

 

By the way, changing the Lane Width to 2 Byte all cores worked.

 

Those who understand the solution, please help me.

 

 

Thank you

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venkata
Moderator
Moderator
867 Views
Registered: ‎02-16-2010

You mention that "It is operating normally in the simulation". Is this applicable to 4-byte lane width setting also?

 

I believe the following should be done on all instances in which "* include Shared Logic in example design : ON" is set. Can you please confirm?

* Single Ended INIT CLK : ON(Only one core)

 

For 4-lane design, whether DRPCLK input is stable?

 

What do you observe on the following status signals?

rx_reset_done_out

tx_reset_done_out

tx_lock

sys_reset_out

soft_err

hard_err

link_reset_out

lane_up

channel_up

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