05-17-2021 09:49 AM
I trying to debug two FPGA that has an Ethernet connection. Each FPGA has a AXI Ethernet System IP and are connected via SGMII interface to an external PHY 1000Base-T SFP copper RJ45 module. Auto-Negotiation is turned ON.
During configuration, I constantly monitored the MDIO Read Data address location 0x508 for the MDIO Ready bit. When this bit is a High, I would read bit 2 and 5 which represent the Link and Auto Negotiation status.
For some reason that I don't understand, it returned the value 0x0001_FFFF, The One represent MDIO Ready =H but what cause all the lower 16-bit to be all High? This shouldn't happened.
05-18-2021 06:02 AM
Hi @tchin123 ,
Have you verified the MDIO clock? Is it working fine and it's a 2.5MHz clock?
05-18-2021 07:04 AM
First thing I did was write to AIX-Ethernet IP at address 0x500 = 0x0000_0068 which is the MDIO setup register to setup the clock.
I know this is working because I was able to R/W to the Internal PHY MDIO registers of the AXI-Ethernet Subsystem IP. As I continue to read the MDIO register 1 for the link and auto-negotiation status during the configuration phase I was getting back some value.
While monitoring the hw_ila signals for the return value for bit 15 which is the MDIO ready bit. When this bit is a High, the lower 16-bit for MDIO register 1 returns all High. Below is the definition for MDIO register 1. This value doesn't make any sense.
05-19-2021 01:19 PM
Any one has any idea on the strange response of getting back all high value for MDIO register 1.
I did some further investigation by reading the MDIO register 4 and 5. I program the auto-neg advertisement MDIO reg4 for 1GB and Duplex. But when I read them back, both reg4 (auto-neg advertisement) and 5 (link partner ability) returned 0x0001 which represent only 10Mbps and half duplex. The strange thing is that since I programmed reg4 with 1Gbps , not sure why it returned 10Mbps
05-20-2021 02:30 PM
Any suggestion on my issue would help!
To add information, I'm using the AXI Ethernet subsystem in SGMII mode and it interface to an external SFP copper RJ45 module. The documentation is very confusing (PG138, PG51 and PG47) concerning the SGMII configuration. It seem like this is considered MAC mode and not PHY mode. This might be the reason why when I read MDIO register 4, it returned 0x0001 which is not what I programmed. I programmed it to advertise 1Gbps and Duplex. PG47 mentioned that when in MAC mode, this register is read only. I try to access the "Auto-Negotiation Configuration Interface" to programmed these auto-negotiation value but the Xilinx IP didn't bring them out to the user.
So now, the device never complete auto-negotiation not attain Link. Please help. anyone ever get this IP to work?
05-26-2021 01:32 AM
Hi @tchin123 ,
As you are having a external PHY SFP, SGMII MAC mode should be used.
I just read your setup again, you have two boards connected back to back? Have you tried to connect one to a PC first and see if the link is up? This could help rule out one link partner issue.
06-23-2021 01:28 AM
Hi @tchin123 ,
Have you made any progress on it?
Can you not access the registers and check if the link is up, and also the traffic should pass when the link is up.