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Ethernet Core file does not have matching formal port.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Ethernet_Controller is
  port (
    core_drp_0_daddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    core_drp_0_den : in STD_LOGIC;
    core_drp_0_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    core_drp_0_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    core_drp_0_drdy : out STD_LOGIC;
    core_drp_0_dwe : in STD_LOGIC;
    core_drp_reset_0 : in STD_LOGIC;
    core_tx_reset_0 : in STD_LOGIC;
    ctl_tx_0_ctl_enable : in STD_LOGIC;
    ctl_tx_0_ctl_test_pattern : in STD_LOGIC;
    ctl_tx_0_ctl_tx_send_idle : in STD_LOGIC;
    ctl_tx_0_ctl_tx_send_lfi : in STD_LOGIC;
    ctl_tx_0_ctl_tx_send_rfi : in STD_LOGIC;
    diff_clock_rtl_clk_n : in STD_LOGIC;
    diff_clock_rtl_clk_p : in STD_LOGIC;
    drp_clk_0 : in STD_LOGIC;
    gt_loopback_in_0 : in STD_LOGIC_VECTOR ( 29 downto 0 );
    gt_powergoodout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_ref_clk_out_0 : out STD_LOGIC;
    gt_rtl_grx_n : in STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rtl_grx_p : in STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rtl_gtx_n : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rtl_gtx_p : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rxrecclkout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_txusrclk2_0 : out STD_LOGIC;
    gtwiz_reset_rx_datapath_0 : in STD_LOGIC;
    gtwiz_reset_tx_datapath_0 : in STD_LOGIC;
    init_clk_0 : in STD_LOGIC;
    lbus_tx_0_lbus_seg0_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    lbus_tx_0_lbus_seg0_ena : in STD_LOGIC;
    lbus_tx_0_lbus_seg0_eop : in STD_LOGIC;
    lbus_tx_0_lbus_seg0_err : in STD_LOGIC;
    lbus_tx_0_lbus_seg0_mty : in STD_LOGIC_VECTOR ( 3 downto 0 );
    lbus_tx_0_lbus_seg0_sop : in STD_LOGIC;
    lbus_tx_0_lbus_seg1_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    lbus_tx_0_lbus_seg1_ena : in STD_LOGIC;
    lbus_tx_0_lbus_seg1_eop : in STD_LOGIC;
    lbus_tx_0_lbus_seg1_err : in STD_LOGIC;
    lbus_tx_0_lbus_seg1_mty : in STD_LOGIC_VECTOR ( 3 downto 0 );
    lbus_tx_0_lbus_seg1_sop : in STD_LOGIC;
    lbus_tx_0_lbus_seg2_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    lbus_tx_0_lbus_seg2_ena : in STD_LOGIC;
    lbus_tx_0_lbus_seg2_eop : in STD_LOGIC;
    lbus_tx_0_lbus_seg2_err : in STD_LOGIC;
    lbus_tx_0_lbus_seg2_mty : in STD_LOGIC_VECTOR ( 3 downto 0 );
    lbus_tx_0_lbus_seg2_sop : in STD_LOGIC;
    lbus_tx_0_lbus_seg3_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    lbus_tx_0_lbus_seg3_ena : in STD_LOGIC;
    lbus_tx_0_lbus_seg3_eop : in STD_LOGIC;
    lbus_tx_0_lbus_seg3_err : in STD_LOGIC;
    lbus_tx_0_lbus_seg3_mty : in STD_LOGIC_VECTOR ( 3 downto 0 );
    lbus_tx_0_lbus_seg3_sop : in STD_LOGIC;
    lbus_tx_0_tx_ovfout : out STD_LOGIC;
    lbus_tx_0_tx_rdyout : out STD_LOGIC;
    lbus_tx_0_tx_unfout : out STD_LOGIC;
    stat_tx_0_stat_tx_bad_fcs : out STD_LOGIC;
    stat_tx_0_stat_tx_broadcast : out STD_LOGIC;
    stat_tx_0_stat_tx_frame_error : out STD_LOGIC;
    stat_tx_0_stat_tx_local_fault : out STD_LOGIC;
    stat_tx_0_stat_tx_multicast : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_1024_1518_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_128_255_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_1519_1522_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_1523_1548_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_1549_2047_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_2048_4095_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_256_511_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_4096_8191_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_512_1023_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_64_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_65_127_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_8192_9215_bytes : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_large : out STD_LOGIC;
    stat_tx_0_stat_tx_packet_small : out STD_LOGIC;
    stat_tx_0_stat_tx_total_bytes : out STD_LOGIC_VECTOR ( 5 downto 0 );
    stat_tx_0_stat_tx_total_good_bytes : out STD_LOGIC_VECTOR ( 13 downto 0 );
    stat_tx_0_stat_tx_total_good_packets : out STD_LOGIC;
    stat_tx_0_stat_tx_total_packets : out STD_LOGIC;
    stat_tx_0_stat_tx_unicast : out STD_LOGIC;
    stat_tx_0_stat_tx_vlan : out STD_LOGIC;
    sys_reset_0 : in STD_LOGIC;
    tx_preamblein_0 : in STD_LOGIC_VECTOR ( 55 downto 0 );
    usr_tx_reset_0 : out STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of Ethernet_Controller : entity is "Ethernet_Controller,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Ethernet_Controller,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_board_cnt=4,da_clkrst_cnt=2,da_cmac_usplus_cnt=1,synth_mode=OOC_per_IP}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of Ethernet_Controller : entity is "Ethernet_Controller.hwdef";
end Ethernet_Controller;

architecture STRUCTURE of Ethernet_Controller is
  component Ethernet_Controller_cmac_usplus_0_0 is
  port (
    gt_txp_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_txn_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rxp_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rxn_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_txusrclk2 : out STD_LOGIC;
    gt_loopback_in : in STD_LOGIC_VECTOR ( 29 downto 0 );
    gt_ref_clk_out : out STD_LOGIC;
    gt_rxrecclkout : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_powergoodout : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gtwiz_reset_tx_datapath : in STD_LOGIC;
    gtwiz_reset_rx_datapath : in STD_LOGIC;
    sys_reset : in STD_LOGIC;
    gt_ref_clk_p : in STD_LOGIC;
    gt_ref_clk_n : in STD_LOGIC;
    init_clk : in STD_LOGIC;
    stat_tx_bad_fcs : out STD_LOGIC;
    stat_tx_broadcast : out STD_LOGIC;
    stat_tx_frame_error : out STD_LOGIC;
    stat_tx_local_fault : out STD_LOGIC;
    stat_tx_multicast : out STD_LOGIC;
    stat_tx_packet_1024_1518_bytes : out STD_LOGIC;
    stat_tx_packet_128_255_bytes : out STD_LOGIC;
    stat_tx_packet_1519_1522_bytes : out STD_LOGIC;
    stat_tx_packet_1523_1548_bytes : out STD_LOGIC;
    stat_tx_packet_1549_2047_bytes : out STD_LOGIC;
    stat_tx_packet_2048_4095_bytes : out STD_LOGIC;
    stat_tx_packet_256_511_bytes : out STD_LOGIC;
    stat_tx_packet_4096_8191_bytes : out STD_LOGIC;
    stat_tx_packet_512_1023_bytes : out STD_LOGIC;
    stat_tx_packet_64_bytes : out STD_LOGIC;
    stat_tx_packet_65_127_bytes : out STD_LOGIC;
    stat_tx_packet_8192_9215_bytes : out STD_LOGIC;
    stat_tx_packet_large : out STD_LOGIC;
    stat_tx_packet_small : out STD_LOGIC;
    stat_tx_total_bytes : out STD_LOGIC_VECTOR ( 5 downto 0 );
    stat_tx_total_good_bytes : out STD_LOGIC_VECTOR ( 13 downto 0 );
    stat_tx_total_good_packets : out STD_LOGIC;
    stat_tx_total_packets : out STD_LOGIC;
    stat_tx_unicast : out STD_LOGIC;
    stat_tx_vlan : out STD_LOGIC;
    ctl_tx_enable : in STD_LOGIC;
    ctl_tx_send_idle : in STD_LOGIC;
    ctl_tx_send_rfi : in STD_LOGIC;
    ctl_tx_send_lfi : in STD_LOGIC;
    ctl_tx_test_pattern : in STD_LOGIC;
    core_tx_reset : in STD_LOGIC;
    tx_ovfout : out STD_LOGIC;
    tx_rdyout : out STD_LOGIC;
    tx_unfout : out STD_LOGIC;
    tx_datain0 : in STD_LOGIC_VECTOR ( 127 downto 0 );
    tx_datain1 : in STD_LOGIC_VECTOR ( 127 downto 0 );
    tx_datain2 : in STD_LOGIC_VECTOR ( 127 downto 0 );
    tx_datain3 : in STD_LOGIC_VECTOR ( 127 downto 0 );
    tx_enain0 : in STD_LOGIC;
    tx_enain1 : in STD_LOGIC;
    tx_enain2 : in STD_LOGIC;
    tx_enain3 : in STD_LOGIC;
    tx_eopin0 : in STD_LOGIC;
    tx_eopin1 : in STD_LOGIC;
    tx_eopin2 : in STD_LOGIC;
    tx_eopin3 : in STD_LOGIC;
    tx_errin0 : in STD_LOGIC;
    tx_errin1 : in STD_LOGIC;
    tx_errin2 : in STD_LOGIC;
    tx_errin3 : in STD_LOGIC;
    tx_mtyin0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_mtyin1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_mtyin2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_mtyin3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_sopin0 : in STD_LOGIC;
    tx_sopin1 : in STD_LOGIC;
    tx_sopin2 : in STD_LOGIC;
    tx_sopin3 : in STD_LOGIC;
    tx_preamblein : in STD_LOGIC_VECTOR ( 55 downto 0 );
    usr_tx_reset : out STD_LOGIC;
    core_drp_reset : in STD_LOGIC;
    drp_clk : in STD_LOGIC;
    drp_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drp_en : in STD_LOGIC;
    drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drp_rdy : out STD_LOGIC;
    drp_we : in STD_LOGIC
  );
  end component Ethernet_Controller_cmac_usplus_0_0;
  signal cmac_usplus_0_gt_powergoodout : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_ref_clk_out : STD_LOGIC;
  signal cmac_usplus_0_gt_rxrecclkout : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_serial_port_GRX_N : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_serial_port_GRX_P : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_serial_port_GTX_N : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_serial_port_GTX_P : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cmac_usplus_0_gt_txusrclk2 : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_bad_fcs : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_broadcast : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_frame_error : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_local_fault : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_multicast : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_1024_1518_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_128_255_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_1519_1522_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_1523_1548_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_1549_2047_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_2048_4095_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_256_511_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_4096_8191_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_512_1023_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_64_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_65_127_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_8192_9215_bytes : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_large : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_packet_small : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_total_bytes : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cmac_usplus_0_stat_tx_stat_tx_total_good_bytes : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal cmac_usplus_0_stat_tx_stat_tx_total_good_packets : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_total_packets : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_unicast : STD_LOGIC;
  signal cmac_usplus_0_stat_tx_stat_tx_vlan : STD_LOGIC;
  signal cmac_usplus_0_usr_tx_reset : STD_LOGIC;
  signal core_drp_0_1_DADDR : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal core_drp_0_1_DEN : STD_LOGIC;
  signal core_drp_0_1_DI : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal core_drp_0_1_DO : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal core_drp_0_1_DRDY : STD_LOGIC;
  signal core_drp_0_1_DWE : STD_LOGIC;
  signal core_drp_reset_0_1 : STD_LOGIC;
  signal core_tx_reset_0_1 : STD_LOGIC;
  signal ctl_tx_0_1_ctl_enable : STD_LOGIC;
  signal ctl_tx_0_1_ctl_test_pattern : STD_LOGIC;
  signal ctl_tx_0_1_ctl_tx_send_idle : STD_LOGIC;
  signal ctl_tx_0_1_ctl_tx_send_lfi : STD_LOGIC;
  signal ctl_tx_0_1_ctl_tx_send_rfi : STD_LOGIC;
  signal diff_clock_rtl_1_CLK_N : STD_LOGIC;
  signal diff_clock_rtl_1_CLK_P : STD_LOGIC;
  signal drp_clk_0_1 : STD_LOGIC;
  signal gt_loopback_in_0_1 : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal gtwiz_reset_rx_datapath_0_1 : STD_LOGIC;
  signal gtwiz_reset_tx_datapath_0_1 : STD_LOGIC;
  signal init_clk_0_1 : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg0_data : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal lbus_tx_0_1_lbus_seg0_ena : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg0_eop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg0_err : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg0_mty : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal lbus_tx_0_1_lbus_seg0_sop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg1_data : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal lbus_tx_0_1_lbus_seg1_ena : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg1_eop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg1_err : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg1_mty : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal lbus_tx_0_1_lbus_seg1_sop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg2_data : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal lbus_tx_0_1_lbus_seg2_ena : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg2_eop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg2_err : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg2_mty : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal lbus_tx_0_1_lbus_seg2_sop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg3_data : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal lbus_tx_0_1_lbus_seg3_ena : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg3_eop : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg3_err : STD_LOGIC;
  signal lbus_tx_0_1_lbus_seg3_mty : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal lbus_tx_0_1_lbus_seg3_sop : STD_LOGIC;
  signal lbus_tx_0_1_tx_ovfout : STD_LOGIC;
  signal lbus_tx_0_1_tx_rdyout : STD_LOGIC;
  signal lbus_tx_0_1_tx_unfout : STD_LOGIC;
  signal sys_reset_0_1 : STD_LOGIC;
  signal tx_preamblein_0_1 : STD_LOGIC_VECTOR ( 55 downto 0 );
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of core_drp_0_den : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DEN";
  attribute X_INTERFACE_INFO of core_drp_0_drdy : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DRDY";
  attribute X_INTERFACE_INFO of core_drp_0_dwe : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DWE";
  attribute X_INTERFACE_INFO of core_drp_reset_0 : signal is "xilinx.com:signal:reset:1.0 RST.CORE_DRP_RESET_0 RST";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of core_drp_reset_0 : signal is "XIL_INTERFACENAME RST.CORE_DRP_RESET_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of core_tx_reset_0 : signal is "xilinx.com:signal:reset:1.0 RST.CORE_TX_RESET_0 RST";
  attribute X_INTERFACE_PARAMETER of core_tx_reset_0 : signal is "XIL_INTERFACENAME RST.CORE_TX_RESET_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of ctl_tx_0_ctl_enable : signal is "xilinx.com:display_cmac_usplus:ctrl_ports_int:2.0 ctl_tx_0 ctl_enable";
  attribute X_INTERFACE_INFO of ctl_tx_0_ctl_test_pattern : signal is "xilinx.com:display_cmac_usplus:ctrl_ports_int:2.0 ctl_tx_0 ctl_test_pattern";
  attribute X_INTERFACE_INFO of ctl_tx_0_ctl_tx_send_idle : signal is "xilinx.com:display_cmac_usplus:ctrl_ports_int:2.0 ctl_tx_0 ctl_tx_send_idle";
  attribute X_INTERFACE_INFO of ctl_tx_0_ctl_tx_send_lfi : signal is "xilinx.com:display_cmac_usplus:ctrl_ports_int:2.0 ctl_tx_0 ctl_tx_send_lfi";
  attribute X_INTERFACE_INFO of ctl_tx_0_ctl_tx_send_rfi : signal is "xilinx.com:display_cmac_usplus:ctrl_ports_int:2.0 ctl_tx_0 ctl_tx_send_rfi";
  attribute X_INTERFACE_INFO of diff_clock_rtl_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 diff_clock_rtl CLK_N";
  attribute X_INTERFACE_PARAMETER of diff_clock_rtl_clk_n : signal is "XIL_INTERFACENAME diff_clock_rtl, CAN_DEBUG false, FREQ_HZ 156250000";
  attribute X_INTERFACE_INFO of diff_clock_rtl_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 diff_clock_rtl CLK_P";
  attribute X_INTERFACE_INFO of drp_clk_0 : signal is "xilinx.com:signal:clock:1.0 CLK.DRP_CLK_0 CLK";
  attribute X_INTERFACE_PARAMETER of drp_clk_0 : signal is "XIL_INTERFACENAME CLK.DRP_CLK_0, ASSOCIATED_RESET core_drp_reset_0, CLK_DOMAIN Ethernet_Controller_drp_clk_0, FREQ_HZ 100000000, PHASE 0.000";
  attribute X_INTERFACE_INFO of gt_ref_clk_out_0 : signal is "xilinx.com:signal:clock:1.0 CLK.GT_REF_CLK_OUT_0 CLK";
  attribute X_INTERFACE_PARAMETER of gt_ref_clk_out_0 : signal is "XIL_INTERFACENAME CLK.GT_REF_CLK_OUT_0, CLK_DOMAIN Ethernet_Controller_cmac_usplus_0_0_gt_ref_clk_out, FREQ_HZ 156250000, PHASE 0.000";
  attribute X_INTERFACE_INFO of gt_txusrclk2_0 : signal is "xilinx.com:signal:clock:1.0 CLK.GT_TXUSRCLK2_0 CLK";
  attribute X_INTERFACE_PARAMETER of gt_txusrclk2_0 : signal is "XIL_INTERFACENAME CLK.GT_TXUSRCLK2_0, CLK_DOMAIN Ethernet_Controller_cmac_usplus_0_0_gt_txusrclk2, FREQ_HZ 322265625, PHASE 0.000";
  attribute X_INTERFACE_INFO of gtwiz_reset_rx_datapath_0 : signal is "xilinx.com:signal:reset:1.0 RST.GTWIZ_RESET_RX_DATAPATH_0 RST";
  attribute X_INTERFACE_PARAMETER of gtwiz_reset_rx_datapath_0 : signal is "XIL_INTERFACENAME RST.GTWIZ_RESET_RX_DATAPATH_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of gtwiz_reset_tx_datapath_0 : signal is "xilinx.com:signal:reset:1.0 RST.GTWIZ_RESET_TX_DATAPATH_0 RST";
  attribute X_INTERFACE_PARAMETER of gtwiz_reset_tx_datapath_0 : signal is "XIL_INTERFACENAME RST.GTWIZ_RESET_TX_DATAPATH_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of init_clk_0 : signal is "xilinx.com:signal:clock:1.0 CLK.INIT_CLK_0 CLK";
  attribute X_INTERFACE_PARAMETER of init_clk_0 : signal is "XIL_INTERFACENAME CLK.INIT_CLK_0, ASSOCIATED_RESET sys_reset_0, CLK_DOMAIN Ethernet_Controller_init_clk_0, FREQ_HZ 100000000, PHASE 0.0";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_ena : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_ena";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_eop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_eop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_err : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_err";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_sop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_sop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_ena : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_ena";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_eop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_eop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_err : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_err";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_sop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_sop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_ena : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_ena";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_eop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_eop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_err : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_err";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_sop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_sop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_ena : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_ena";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_eop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_eop";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_err : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_err";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_sop : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_sop";
  attribute X_INTERFACE_INFO of lbus_tx_0_tx_ovfout : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 tx_ovfout";
  attribute X_INTERFACE_INFO of lbus_tx_0_tx_rdyout : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 tx_rdyout";
  attribute X_INTERFACE_INFO of lbus_tx_0_tx_unfout : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 tx_unfout";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_bad_fcs : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_bad_fcs";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_broadcast : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_broadcast";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_frame_error : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_frame_error";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_local_fault : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_local_fault";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_multicast : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_multicast";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_1024_1518_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_1024_1518_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_128_255_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_128_255_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_1519_1522_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_1519_1522_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_1523_1548_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_1523_1548_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_1549_2047_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_1549_2047_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_2048_4095_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_2048_4095_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_256_511_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_256_511_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_4096_8191_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_4096_8191_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_512_1023_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_512_1023_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_64_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_64_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_65_127_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_65_127_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_8192_9215_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_8192_9215_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_large : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_large";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_packet_small : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_packet_small";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_total_good_packets : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_total_good_packets";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_total_packets : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_total_packets";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_unicast : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_unicast";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_vlan : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_vlan";
  attribute X_INTERFACE_INFO of sys_reset_0 : signal is "xilinx.com:signal:reset:1.0 RST.SYS_RESET_0 RST";
  attribute X_INTERFACE_PARAMETER of sys_reset_0 : signal is "XIL_INTERFACENAME RST.SYS_RESET_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of usr_tx_reset_0 : signal is "xilinx.com:signal:reset:1.0 RST.USR_TX_RESET_0 RST";
  attribute X_INTERFACE_PARAMETER of usr_tx_reset_0 : signal is "XIL_INTERFACENAME RST.USR_TX_RESET_0, POLARITY ACTIVE_HIGH";
  attribute X_INTERFACE_INFO of core_drp_0_daddr : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DADDR";
  attribute X_INTERFACE_INFO of core_drp_0_di : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DI";
  attribute X_INTERFACE_INFO of core_drp_0_do : signal is "xilinx.com:interface:drp:1.0 core_drp_0 DO";
  attribute X_INTERFACE_INFO of gt_rtl_grx_n : signal is "xilinx.com:interface:gt:1.0 gt_rtl GRX_N";
  attribute X_INTERFACE_PARAMETER of gt_rtl_grx_n : signal is "XIL_INTERFACENAME gt_rtl, CAN_DEBUG false";
  attribute X_INTERFACE_INFO of gt_rtl_grx_p : signal is "xilinx.com:interface:gt:1.0 gt_rtl GRX_P";
  attribute X_INTERFACE_INFO of gt_rtl_gtx_n : signal is "xilinx.com:interface:gt:1.0 gt_rtl GTX_N";
  attribute X_INTERFACE_INFO of gt_rtl_gtx_p : signal is "xilinx.com:interface:gt:1.0 gt_rtl GTX_P";
  attribute X_INTERFACE_INFO of gt_rxrecclkout_0 : signal is "xilinx.com:signal:clock:1.0 CLK.GT_RXRECCLKOUT_0 CLK";
  attribute X_INTERFACE_PARAMETER of gt_rxrecclkout_0 : signal is "XIL_INTERFACENAME CLK.GT_RXRECCLKOUT_0, CLK_DOMAIN Ethernet_Controller_cmac_usplus_0_0_gt_rxrecclkout, FREQ_HZ 322265625, PHASE 0.000";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_data : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_data";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg0_mty : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg0_mty";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_data : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_data";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg1_mty : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg1_mty";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_data : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_data";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg2_mty : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg2_mty";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_data : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_data";
  attribute X_INTERFACE_INFO of lbus_tx_0_lbus_seg3_mty : signal is "xilinx.com:display_cmac_usplus:lbus_ports_int:2.0 lbus_tx_0 lbus_seg3_mty";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_total_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_total_bytes";
  attribute X_INTERFACE_INFO of stat_tx_0_stat_tx_total_good_bytes : signal is "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0 stat_tx_0 stat_tx_total_good_bytes";
begin
  cmac_usplus_0_gt_serial_port_GRX_N(9 downto 0) <= gt_rtl_grx_n(9 downto 0);
  cmac_usplus_0_gt_serial_port_GRX_P(9 downto 0) <= gt_rtl_grx_p(9 downto 0);
  core_drp_0_1_DADDR(9 downto 0) <= core_drp_0_daddr(9 downto 0);
  core_drp_0_1_DEN <= core_drp_0_den;
  core_drp_0_1_DI(15 downto 0) <= core_drp_0_di(15 downto 0);
  core_drp_0_1_DWE <= core_drp_0_dwe;
  core_drp_0_do(15 downto 0) <= core_drp_0_1_DO(15 downto 0);
  core_drp_0_drdy <= core_drp_0_1_DRDY;
  core_drp_reset_0_1 <= core_drp_reset_0;
  core_tx_reset_0_1 <= core_tx_reset_0;
  ctl_tx_0_1_ctl_enable <= ctl_tx_0_ctl_enable;
  ctl_tx_0_1_ctl_test_pattern <= ctl_tx_0_ctl_test_pattern;
  ctl_tx_0_1_ctl_tx_send_idle <= ctl_tx_0_ctl_tx_send_idle;
  ctl_tx_0_1_ctl_tx_send_lfi <= ctl_tx_0_ctl_tx_send_lfi;
  ctl_tx_0_1_ctl_tx_send_rfi <= ctl_tx_0_ctl_tx_send_rfi;
  diff_clock_rtl_1_CLK_N <= diff_clock_rtl_clk_n;
  diff_clock_rtl_1_CLK_P <= diff_clock_rtl_clk_p;
  drp_clk_0_1 <= drp_clk_0;
  gt_loopback_in_0_1(29 downto 0) <= gt_loopback_in_0(29 downto 0);
  gt_powergoodout_0(9 downto 0) <= cmac_usplus_0_gt_powergoodout(9 downto 0);
  gt_ref_clk_out_0 <= cmac_usplus_0_gt_ref_clk_out;
  gt_rtl_gtx_n(9 downto 0) <= cmac_usplus_0_gt_serial_port_GTX_N(9 downto 0);
  gt_rtl_gtx_p(9 downto 0) <= cmac_usplus_0_gt_serial_port_GTX_P(9 downto 0);
  gt_rxrecclkout_0(9 downto 0) <= cmac_usplus_0_gt_rxrecclkout(9 downto 0);
  gt_txusrclk2_0 <= cmac_usplus_0_gt_txusrclk2;
  gtwiz_reset_rx_datapath_0_1 <= gtwiz_reset_rx_datapath_0;
  gtwiz_reset_tx_datapath_0_1 <= gtwiz_reset_tx_datapath_0;
  init_clk_0_1 <= init_clk_0;
  lbus_tx_0_1_lbus_seg0_data(127 downto 0) <= lbus_tx_0_lbus_seg0_data(127 downto 0);
  lbus_tx_0_1_lbus_seg0_ena <= lbus_tx_0_lbus_seg0_ena;
  lbus_tx_0_1_lbus_seg0_eop <= lbus_tx_0_lbus_seg0_eop;
  lbus_tx_0_1_lbus_seg0_err <= lbus_tx_0_lbus_seg0_err;
  lbus_tx_0_1_lbus_seg0_mty(3 downto 0) <= lbus_tx_0_lbus_seg0_mty(3 downto 0);
  lbus_tx_0_1_lbus_seg0_sop <= lbus_tx_0_lbus_seg0_sop;
  lbus_tx_0_1_lbus_seg1_data(127 downto 0) <= lbus_tx_0_lbus_seg1_data(127 downto 0);
  lbus_tx_0_1_lbus_seg1_ena <= lbus_tx_0_lbus_seg1_ena;
  lbus_tx_0_1_lbus_seg1_eop <= lbus_tx_0_lbus_seg1_eop;
  lbus_tx_0_1_lbus_seg1_err <= lbus_tx_0_lbus_seg1_err;
  lbus_tx_0_1_lbus_seg1_mty(3 downto 0) <= lbus_tx_0_lbus_seg1_mty(3 downto 0);
  lbus_tx_0_1_lbus_seg1_sop <= lbus_tx_0_lbus_seg1_sop;
  lbus_tx_0_1_lbus_seg2_data(127 downto 0) <= lbus_tx_0_lbus_seg2_data(127 downto 0);
  lbus_tx_0_1_lbus_seg2_ena <= lbus_tx_0_lbus_seg2_ena;
  lbus_tx_0_1_lbus_seg2_eop <= lbus_tx_0_lbus_seg2_eop;
  lbus_tx_0_1_lbus_seg2_err <= lbus_tx_0_lbus_seg2_err;
  lbus_tx_0_1_lbus_seg2_mty(3 downto 0) <= lbus_tx_0_lbus_seg2_mty(3 downto 0);
  lbus_tx_0_1_lbus_seg2_sop <= lbus_tx_0_lbus_seg2_sop;
  lbus_tx_0_1_lbus_seg3_data(127 downto 0) <= lbus_tx_0_lbus_seg3_data(127 downto 0);
  lbus_tx_0_1_lbus_seg3_ena <= lbus_tx_0_lbus_seg3_ena;
  lbus_tx_0_1_lbus_seg3_eop <= lbus_tx_0_lbus_seg3_eop;
  lbus_tx_0_1_lbus_seg3_err <= lbus_tx_0_lbus_seg3_err;
  lbus_tx_0_1_lbus_seg3_mty(3 downto 0) <= lbus_tx_0_lbus_seg3_mty(3 downto 0);
  lbus_tx_0_1_lbus_seg3_sop <= lbus_tx_0_lbus_seg3_sop;
  lbus_tx_0_tx_ovfout <= lbus_tx_0_1_tx_ovfout;
  lbus_tx_0_tx_rdyout <= lbus_tx_0_1_tx_rdyout;
  lbus_tx_0_tx_unfout <= lbus_tx_0_1_tx_unfout;
  stat_tx_0_stat_tx_bad_fcs <= cmac_usplus_0_stat_tx_stat_tx_bad_fcs;
  stat_tx_0_stat_tx_broadcast <= cmac_usplus_0_stat_tx_stat_tx_broadcast;
  stat_tx_0_stat_tx_frame_error <= cmac_usplus_0_stat_tx_stat_tx_frame_error;
  stat_tx_0_stat_tx_local_fault <= cmac_usplus_0_stat_tx_stat_tx_local_fault;
  stat_tx_0_stat_tx_multicast <= cmac_usplus_0_stat_tx_stat_tx_multicast;
  stat_tx_0_stat_tx_packet_1024_1518_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_1024_1518_bytes;
  stat_tx_0_stat_tx_packet_128_255_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_128_255_bytes;
  stat_tx_0_stat_tx_packet_1519_1522_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_1519_1522_bytes;
  stat_tx_0_stat_tx_packet_1523_1548_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_1523_1548_bytes;
  stat_tx_0_stat_tx_packet_1549_2047_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_1549_2047_bytes;
  stat_tx_0_stat_tx_packet_2048_4095_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_2048_4095_bytes;
  stat_tx_0_stat_tx_packet_256_511_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_256_511_bytes;
  stat_tx_0_stat_tx_packet_4096_8191_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_4096_8191_bytes;
  stat_tx_0_stat_tx_packet_512_1023_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_512_1023_bytes;
  stat_tx_0_stat_tx_packet_64_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_64_bytes;
  stat_tx_0_stat_tx_packet_65_127_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_65_127_bytes;
  stat_tx_0_stat_tx_packet_8192_9215_bytes <= cmac_usplus_0_stat_tx_stat_tx_packet_8192_9215_bytes;
  stat_tx_0_stat_tx_packet_large <= cmac_usplus_0_stat_tx_stat_tx_packet_large;
  stat_tx_0_stat_tx_packet_small <= cmac_usplus_0_stat_tx_stat_tx_packet_small;
  stat_tx_0_stat_tx_total_bytes(5 downto 0) <= cmac_usplus_0_stat_tx_stat_tx_total_bytes(5 downto 0);
  stat_tx_0_stat_tx_total_good_bytes(13 downto 0) <= cmac_usplus_0_stat_tx_stat_tx_total_good_bytes(13 downto 0);
  stat_tx_0_stat_tx_total_good_packets <= cmac_usplus_0_stat_tx_stat_tx_total_good_packets;
  stat_tx_0_stat_tx_total_packets <= cmac_usplus_0_stat_tx_stat_tx_total_packets;
  stat_tx_0_stat_tx_unicast <= cmac_usplus_0_stat_tx_stat_tx_unicast;
  stat_tx_0_stat_tx_vlan <= cmac_usplus_0_stat_tx_stat_tx_vlan;
  sys_reset_0_1 <= sys_reset_0;
  tx_preamblein_0_1(55 downto 0) <= tx_preamblein_0(55 downto 0);
  usr_tx_reset_0 <= cmac_usplus_0_usr_tx_reset;
cmac_usplus_0: component Ethernet_Controller_cmac_usplus_0_0
     port map (
      core_drp_reset => core_drp_reset_0_1,
      core_tx_reset => core_tx_reset_0_1,
      ctl_tx_enable => ctl_tx_0_1_ctl_enable,
      ctl_tx_send_idle => ctl_tx_0_1_ctl_tx_send_idle,
      ctl_tx_send_lfi => ctl_tx_0_1_ctl_tx_send_lfi,
      ctl_tx_send_rfi => ctl_tx_0_1_ctl_tx_send_rfi,
      ctl_tx_test_pattern => ctl_tx_0_1_ctl_test_pattern,
      drp_addr(9 downto 0) => core_drp_0_1_DADDR(9 downto 0),
      drp_clk => drp_clk_0_1,
      drp_di(15 downto 0) => core_drp_0_1_DI(15 downto 0),
      drp_do(15 downto 0) => core_drp_0_1_DO(15 downto 0),
      drp_en => core_drp_0_1_DEN,
      drp_rdy => core_drp_0_1_DRDY,
      drp_we => core_drp_0_1_DWE,
      gt_loopback_in(29 downto 0) => gt_loopback_in_0_1(29 downto 0),
      gt_powergoodout(9 downto 0) => cmac_usplus_0_gt_powergoodout(9 downto 0),
      gt_ref_clk_n => diff_clock_rtl_1_CLK_N,
      gt_ref_clk_out => cmac_usplus_0_gt_ref_clk_out,
      gt_ref_clk_p => diff_clock_rtl_1_CLK_P,
      gt_rxn_in(9 downto 0) => cmac_usplus_0_gt_serial_port_GRX_N(9 downto 0), -- Doesn't like this
      gt_rxp_in(9 downto 0) => cmac_usplus_0_gt_serial_port_GRX_P(9 downto 0), -- Doesn't like this
      gt_rxrecclkout(9 downto 0) => cmac_usplus_0_gt_rxrecclkout(9 downto 0),
      gt_txn_out(9 downto 0) => cmac_usplus_0_gt_serial_port_GTX_N(9 downto 0),
      gt_txp_out(9 downto 0) => cmac_usplus_0_gt_serial_port_GTX_P(9 downto 0),
      gt_txusrclk2 => cmac_usplus_0_gt_txusrclk2,
      gtwiz_reset_rx_datapath => gtwiz_reset_rx_datapath_0_1,
      gtwiz_reset_tx_datapath => gtwiz_reset_tx_datapath_0_1,
      init_clk => init_clk_0_1,
      stat_tx_bad_fcs => cmac_usplus_0_stat_tx_stat_tx_bad_fcs,
      stat_tx_broadcast => cmac_usplus_0_stat_tx_stat_tx_broadcast,
      stat_tx_frame_error => cmac_usplus_0_stat_tx_stat_tx_frame_error,
      stat_tx_local_fault => cmac_usplus_0_stat_tx_stat_tx_local_fault,
      stat_tx_multicast => cmac_usplus_0_stat_tx_stat_tx_multicast,
      stat_tx_packet_1024_1518_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_1024_1518_bytes,
      stat_tx_packet_128_255_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_128_255_bytes,
      stat_tx_packet_1519_1522_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_1519_1522_bytes,
      stat_tx_packet_1523_1548_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_1523_1548_bytes,
      stat_tx_packet_1549_2047_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_1549_2047_bytes,
      stat_tx_packet_2048_4095_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_2048_4095_bytes,
      stat_tx_packet_256_511_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_256_511_bytes,
      stat_tx_packet_4096_8191_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_4096_8191_bytes,
      stat_tx_packet_512_1023_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_512_1023_bytes,
      stat_tx_packet_64_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_64_bytes,
      stat_tx_packet_65_127_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_65_127_bytes,
      stat_tx_packet_8192_9215_bytes => cmac_usplus_0_stat_tx_stat_tx_packet_8192_9215_bytes,
      stat_tx_packet_large => cmac_usplus_0_stat_tx_stat_tx_packet_large,
      stat_tx_packet_small => cmac_usplus_0_stat_tx_stat_tx_packet_small,
      stat_tx_total_bytes(5 downto 0) => cmac_usplus_0_stat_tx_stat_tx_total_bytes(5 downto 0),
      stat_tx_total_good_bytes(13 downto 0) => cmac_usplus_0_stat_tx_stat_tx_total_good_bytes(13 downto 0),
      stat_tx_total_good_packets => cmac_usplus_0_stat_tx_stat_tx_total_good_packets,
      stat_tx_total_packets => cmac_usplus_0_stat_tx_stat_tx_total_packets,
      stat_tx_unicast => cmac_usplus_0_stat_tx_stat_tx_unicast,
      stat_tx_vlan => cmac_usplus_0_stat_tx_stat_tx_vlan,
      sys_reset => sys_reset_0_1,
      tx_datain0(127 downto 0) => lbus_tx_0_1_lbus_seg0_data(127 downto 0),
      tx_datain1(127 downto 0) => lbus_tx_0_1_lbus_seg1_data(127 downto 0),
      tx_datain2(127 downto 0) => lbus_tx_0_1_lbus_seg2_data(127 downto 0),
      tx_datain3(127 downto 0) => lbus_tx_0_1_lbus_seg3_data(127 downto 0),
      tx_enain0 => lbus_tx_0_1_lbus_seg0_ena,
      tx_enain1 => lbus_tx_0_1_lbus_seg1_ena,
      tx_enain2 => lbus_tx_0_1_lbus_seg2_ena,
      tx_enain3 => lbus_tx_0_1_lbus_seg3_ena,
      tx_eopin0 => lbus_tx_0_1_lbus_seg0_eop,
      tx_eopin1 => lbus_tx_0_1_lbus_seg1_eop,
      tx_eopin2 => lbus_tx_0_1_lbus_seg2_eop,
      tx_eopin3 => lbus_tx_0_1_lbus_seg3_eop,
      tx_errin0 => lbus_tx_0_1_lbus_seg0_err,
      tx_errin1 => lbus_tx_0_1_lbus_seg1_err,
      tx_errin2 => lbus_tx_0_1_lbus_seg2_err,
      tx_errin3 => lbus_tx_0_1_lbus_seg3_err,
      tx_mtyin0(3 downto 0) => lbus_tx_0_1_lbus_seg0_mty(3 downto 0),
      tx_mtyin1(3 downto 0) => lbus_tx_0_1_lbus_seg1_mty(3 downto 0),
      tx_mtyin2(3 downto 0) => lbus_tx_0_1_lbus_seg2_mty(3 downto 0),
      tx_mtyin3(3 downto 0) => lbus_tx_0_1_lbus_seg3_mty(3 downto 0),
      tx_ovfout => lbus_tx_0_1_tx_ovfout,
      tx_preamblein(55 downto 0) => tx_preamblein_0_1(55 downto 0),
      tx_rdyout => lbus_tx_0_1_tx_rdyout,
      tx_sopin0 => lbus_tx_0_1_lbus_seg0_sop,
      tx_sopin1 => lbus_tx_0_1_lbus_seg1_sop,
      tx_sopin2 => lbus_tx_0_1_lbus_seg2_sop,
      tx_sopin3 => lbus_tx_0_1_lbus_seg3_sop,
      tx_unfout => lbus_tx_0_1_tx_unfout,
      usr_tx_reset => cmac_usplus_0_usr_tx_reset
    );
end STRUCTURE;

I'm working on using a simple TX only ethernet core and the synthesis fails with error [ Synth 8-3494]. My question is why does the ip block of the ethernet keep the gt_rx n and p ports even though it is only transmitting data. Also, its in the actual core files where the error occurs. I'm using the 100G ultrascale ethernet version 2.4. Capture.PNG

 

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Visitor
Visitor
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Registered: ‎02-05-2020

Re: Ethernet Core file does not have matching formal port.

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I ended up fixing this by going into the <bd_design_name>_c_usplus_0_0.v file and updating the top port list to include the gt_rxp_in and gt_rxn_in signals and seting the corresponding values in my top entity to 0.

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Visitor
Visitor
144 Views
Registered: ‎02-05-2020

Re: Ethernet Core file does not have matching formal port.

Jump to solution

I ended up fixing this by going into the <bd_design_name>_c_usplus_0_0.v file and updating the top port list to include the gt_rxp_in and gt_rxn_in signals and seting the corresponding values in my top entity to 0.

View solution in original post