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Registered: ‎10-28-2020

Ethernet demo stuck at while (!FramesRx) - loop back disable

I am trying to bring up Ethernet IP by sending a package from the FPGA to my PC. Vivado version 2019.1, FPGA Zynq-7000 Zedboard I follow the instruction in



First, the software stuck at auto-negotiation and I fixed it by setting bit-12 in Register0 (auto negotiation enabled). Once it fixed, the phy works and I can see the package in the WireShark software from PC to the FPGA, but no package from FPGA to PC.
The software stuck at waiting for Rx interrupt, in this line (xemacps_example_intr_dma.c):

\* Wait for Rx indication */

while (!FramesRx);


Does anyone has this issue before? Please help!

This is the third part of the zynq soc gigabit Ethernet series and covers the explanation of the SDK code.Check out the introduction/first part if you aren't...
This is the final part of the zynq soc gigabit Ethernet series and covers the execution of the code. I have also covered the disabling of the loopback mode i...
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Registered: ‎08-25-2009

Hi @Abdulwahhab ,

This "xemacps_example_intr_dma.c" example design is simply sending one packet from the TX and looping it back through the PHY on the RX to generate an interrupt. 

As you said you disabled loopback, it will then wait on the RX direction to receive that frame thus it hangs. 

If you'd like to receive the packet on the PC rather than loop it back, you will need to modify the codes or you may want to try with lwip echo example instead. 


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