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Visitor ferniebola
Visitor
243 Views
Registered: ‎02-28-2019

Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

I have a custom board with an Ethernet PHY connected to the Zynq-7000 ETH0 through the MIO. I cannot get it to work with Ubunt Linux and everything seems to point to a misconfiguration in the device tree. Is out there any example design like this one and a device tree example? If not; could I consult with a Xilinx Ethernet expert for the design?

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7 Replies
Moderator
Moderator
211 Views
Registered: ‎08-25-2009

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hi @ferniebola ,

Can you please post your device tree here? What is not working? Can you see the ethernet interface up but not able to ping? Or you cannot see it even up?

Please make sure you have used below in DTS and enabled TX and RX skew in the PHY.

phy-mode = "rgmii-id";

 

 

"Don't forget to reply, kudo and accept as solution."
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Visitor ferniebola
Visitor
185 Views
Registered: ‎02-28-2019

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hello Nanz,

I downloaded the Xilinx device tree generation master repository and added it to the SDK as a "Global Repository. Then I created a new "Board Support Packge" of type "device_tree".

Then I added some information to the Ethernet node. I am attaching a WinZip-compressed version of such device tree BSP.

In my hardware I can see the Ethernet LED blinking on the LAN magjack but when I power on my board; which is a custom daughter card to the Krtkl Snickerdoodle-Black board, and boot Ubuntu Linux the output from the boot reads:

[  OK  ] Dispatcher daemon for systemd-networkd.
[ ***  ] A start job is running for Raise network interfaces (10s / 21s).

and then...

[FAILED] Failed to start Raise network interfaces.

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Visitor ferniebola
Visitor
180 Views
Registered: ‎02-28-2019

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hello again, Nanz,

In the process of trying and re-trying I noticed that the U-Boot is indicating that the ethernet cannot be found. This is the output from the U-Boot:

U-Boot 2018.01-snickerdoodle-13918-gb1975fd66c (Sep 06 2018 - 11:07:30 -0700)

Model: snickerdoodle Black
Board: Xilinx Zynq
Silicon: v3.1
DRAM: ECC disabled 1 GiB
MMC: sdhci@e0100000: 0 (SD)
Using default environment

In: serial@e0000000
Out: serial@e0000000
Err: serial@e0000000
Net: No ethernet found.
reading uEnv.txt
408 bytes read in 9 ms (43.9 KiB/s)
Importing environment from SD ...
Hit any key to stop autoboot: 0
Device: sdhci@e0100000
Manufacturer ID: 27
OEM: 5048
Name: SD16G
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
reading uEnv.txt
408 bytes read in 9 ms (43.9 KiB/s)
Loaded environment from uEnv.txt
Importing environment from SD ...
Running uenvcmd ...
reading uboot.scr
750 bytes read in 11 ms (66.4 KiB/s)
## Executing script at 04000000
Loading bitstream from system.bit
reading system.bit

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Moderator
Moderator
146 Views
Registered: ‎08-25-2009

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hi @ferniebola ,

I could not find system-user.dtsi in the files that you attached. Can you please send it? Are you sure that the driver has been enabled in the kernel?

 

 

"Don't forget to reply, kudo and accept as solution."
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Visitor ferniebola
Visitor
130 Views
Registered: ‎02-28-2019

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hello Nanz,

I am a little confused; why are you looking for a file called syste-user.dtsi? The only files that I included are:

|-> system-top.dts
   |-> zynq-7000.dtsi
   |-> pcw.dtsi

I modified pcw.dtsi by adding the line "local-mac-address = [00 0a 35 00 00 00];" in the section:

&gem0 {
   phy-mode = "rgmii-id";
   status = "okay";
   xlnx,ptp-enet-clock = <0x89c0c1b>;
   local-mac-address = [00 0a 35 00 00 00];
};

For the Linux Kernel I used the exact same Linux image that is used with an off-the-shelf board called Snickerdoodle-black and piSmasher. These combination of boards uses the exact same Ethernet PHY that I put in my board (think of my board as a replacement for piSmasher with the difference that the PHY is connected to the MIO in my board instead of to the EMIO in piShmasher). So; unless I am not understanding how the Kernel configuraiton works (which is quite possible); I was expecting that the drivers would already be included in the image.

Or maybe I just need to be educated in the process of configuring a Linux image from ground zero for my design and then generating the appropriate device tree for it. Is there any documentation or application note that guides through the whole process?

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Moderator
Moderator
109 Views
Registered: ‎08-25-2009

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hi  @ferniebola ,

The system-user.dtsi is normally the one for modification with adding customers' DTS configuration.I would recommend taking a look at XAPP1305 (though it's for ZU+) which has an exmaple of using GEM3 + RGMII through MIO.

https://www.xilinx.com/support/documentation/application_notes/xapp1305-ps-pl-based-ethernet-solution.pdf

To start up with Linux, here is the blog post which might be very useful.

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Introduction-to-PetaLinux-Part-One/ba-p/968413

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Introduction-To-PetaLinux-Part-2/ba-p/1001124

 

 

"Don't forget to reply, kudo and accept as solution."
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Visitor ferniebola
Visitor
82 Views
Registered: ‎02-28-2019

Re: Example design for Zynq-7000 with Ethernet routed through the MIO (ETH0) including device tree

Hello Nanz,

Thank you for the links. Here is an update:

I read XAPP1305 and downloaded the reference design that it points to. I found out some inconsistencies.

The PDF of XAPP1305 points to a place in the Xilinx Wiki that describes the files in the reference design (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841830/PS+and+PL+based+Ethernet+in+Zynq+MPSoC#PSandPLbasedEthernetinZynqMPSoC-2.XAPP1305). The Wiki indicates this (copied directly from the Wiki)

( for PS_MIO design,navigate to hardware/vivado/scripts/ps_eth_1g and run 'vivado source ps_eth_1g_top.tcl' ,
rest of the steps remain the same)

However; neither the ps_eth_1g folder nor the ps_eth_1g_top.tcl script can be found in the reference design files.The following are the only examples that can be found in the reference design:

pl_eth_1G
pl_eth_10G
pl_eth_sgmii
ps_emio_eth_1G
ps_emio_eth_sgmii

I ran the TCL script of each and everyone of those examples and opened the block designs and the only one that utilizes the MIO for Ethernet is pl_eth_10G.

And this is where I am now. Next I will be analyzing the pl_eth_10G design and looking at the links for generating U-BOOT and Linux for Zynq that you sent me. 

I will keep you posted.

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