I am trying to send data through ethernet via GEM interface. The data is being generated by an FPGA block,
however I haven't been able to put it into the GEM FIFO, as the packets are not reaching the destination.
I believe the communication between host and client is not the problem, as both ethernet interfaces have a valid link and I managed to succesfully send data over a socket, using a python script in linux.
How can I check/manipulate the FIFO content to be sure that I am dealing with it accordingly regarding the FPGA side? Which registers should I configure to send data through GEM External FIFO and which one should I read to check if the FIFO is receiving data correctly from FPGA logic?