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lucas.manco
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Visitor
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Registered: ‎01-09-2019

GEM External FIFO Configuration

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Hello,

I am trying to send data through ethernet via GEM interface. The data is being generated by an FPGA block,

however I haven't been able to put it into the GEM FIFO, as the packets are not reaching the destination.

I believe the communication between host and client is not the problem, as both ethernet interfaces have a valid link and I managed to succesfully send data over a socket, using a python script in linux.

How can I check/manipulate the FIFO content to be sure that I am dealing with it accordingly regarding the FPGA side? Which registers should I configure to send data through GEM External FIFO and which one should I read to check if the FIFO is receiving data correctly from FPGA logic?

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nanz
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Moderator
507 Views
Registered: ‎08-25-2009

Hi @lucas.manco ,

Could you please check https://www.xilinx.com/support/answers/69490.html 1) and see if that helps?

UG1085 does have a section talking about how external FIFO interface works too.

 


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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1 Reply
nanz
Moderator
Moderator
508 Views
Registered: ‎08-25-2009

Hi @lucas.manco ,

Could you please check https://www.xilinx.com/support/answers/69490.html 1) and see if that helps?

UG1085 does have a section talking about how external FIFO interface works too.

 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post