05-06-2014 03:03 AM
I need to check GTP link integrity on AC701 board. I read document xtp224.pdf (AC701 GTP IBERT Design Creation) while using vivado 2013.3.
I downloaded RDF0222 - AC701 GTP IBERT Design Files (2013.3 C) zip and did waht was written in xtp224.pdf
In the design folder, i noted in xdc file that no lines are there to connect TXP,TXN with RXP and RXN respectively.
In serial IO analyzer layout mode, the link is up with 6.25 gbps while there is no loopback.
Link is up : for near end PCS and PMA loopback modes.
no link : when far end PCS and far end PMA loopbacks are done.
Can anyone tell me do i need to put TX,RX pin locations in xdc file or if somethiing else is wrong?
05-06-2014 03:12 AM
05-06-2014 03:13 AM
Verify whether you are applying reset in IBERT after changing entries.
Also use IBERT design assistant ARhttp://www.xilinx.com/support/answers/33793.html to solve the issue
Also the following AR http://www.xilinx.com/support/answers/54139.html helps to verify switch and & jumper settings and to check board problems if exists
05-06-2014 04:13 AM
05-06-2014 04:57 AM
The FAR end loopback mode does not work for a single TX and RX. the FAR end loopback modes indicate a loopback as TX(FPGA1)-> RX(FPGA2) - > looped back through either PCS/PMA -> TX(FPGA2) -> back into the RX(FPGA1 where frame check is done)
By connecting a TXP/N to the RXP/N, you are just looping back externally. You should give the mode as "None" to check for the external loopback. Check and let me know if the None mode does not show the required line rate.
05-06-2014 06:09 AM
I need to iimplement aurora core on AC701.
TXRESETDONE and RXRESETDONE are 1 but channel_up and lane_up are 0. Can this be related to link training or something related to link?
05-06-2014 10:43 PM
Since the IBERT shows the link is up, that means the data is being recived correctly at the RX irrespective of the BER values. You can depend on the IBERT test on the signal integrity of the link. On the Aurora Problem, did you simulate your design and check? Does the simulation also show the lane up/channel up as 0?
05-06-2014 11:51 PM
I ran simulation in questasim for 3000 microseconds and results are same. tx and rx resetdone are high and lane up and channel up low. The only change in example design is that i have given init_clk to the design which is generated by a pll (125 MHz input, 50 MHz output) and not from fpga pins
05-14-2014 11:39 PM
05-15-2014 01:32 AM
05-15-2014 04:34 AM
05-15-2014 06:11 AM
I am attaching the waveform. Magenta are states of lane_init_sm. While tracking the RESET back, it is coming from channel_init_sm and responsible signals are in yellow color.