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dimitris78
Adventurer
Adventurer
566 Views
Registered: ‎09-13-2019

GTRefClk and TX/RX user clock relationship in Ethernet 100G IP

My understanding is in the Ethernet 100G IP the TX and RX user clocks are the same frequency as the GTRefClk. Is there a way to change the frequency relationship ?

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guozhenp
Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎05-01-2013

Do you mean hard CMAC? PG203 has suggested that TX/RX CLK should be 322.266MHz

Why do you want to change them?

 

https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v3_0/pg203-cmac-usplus.pdf

 

TX CLK
This clock is provided to both the CMAC block and serial transceiver to clock the GT/ lane
logic TX interface as well as the whole Ethernet MAC. The clock must be 322.266 MHz for
both CAUI-10, CAUI-4, and 100GAUI-2 operation. The GT lane logic interface datapath is 32
bits per lane for CAUI-10 and 80 bits per lane for CAUI-4 and 100GAUI-2. Only one TX_CLK
is needed regardless of the CAUI-10 or CAUI-4 implementation. This clock also clocks the
transmit Ethernet MAC, LBUS/AXIS interface, and the Control/Status port.


RX CLK
This clock is provided to the CMAC block. The clock must be 322.266 MHz for both CAUI-10,
CAUI-4, and 100GAUI-2 operation, and must be the same as TX_CLK. This clock is used in
the receive Ethernet MAC, LBUS/AXIS interface, and the Control/Status port.

dimitris78
Adventurer
Adventurer
524 Views
Registered: ‎09-13-2019

hi @guozhenp,

Yes the hard MAC in an Eth 100G IP core. 

I tried to test a large design on a Virtex US fpga and with 322M gtrefclk there were timing violations.

On a custom board that hosts a Kintex timing will pass with 156.25M gtrefclk/txclk. TX clock of 195M would be preferable but timing closure might be uncertain.

If the txclk frequency can be tuned w.r.t the gtrefclk then the gtrefclk board oscillator can be set to 156.25 and the txclk can then be altered later in the IP config if timing can be met.

 

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