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Visitor rs-sit_berl
Visitor
259 Views
Registered: ‎08-19-2019

HOLDOVER clock for synchronous ethernet

Hi,

I have to realize a holdover clock mechanism based on a STRATUM3 clock input. I realized a working SyncE clock to the TX transceiver through the PICXO IP core.

In case of HOLDOVER I like to switch a new reference clock to PICXO  based on last good RX transceiver CDR phase. I don't have any PLL hardware outside (like Silabs 53xx ... )   and I thought it could be done with kind of oversampling based on STRATUM3 clock or so.  Is there any other method or any ideas to do it inside the FPGA ?  With my oversampling method I'm not passing the SyncE Hold test on Calnex ...

Thanks !!! 

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3 Replies
Xilinx Employee
Xilinx Employee
132 Views
Registered: ‎08-25-2010

回复: HOLDOVER clock for synchronous ethernet

Hi @rs-sit_berl 

Do you have a planed clock scheme? It seems this is a transceiver issue.

Thanks
Simon
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Visitor rs-sit_berl
Visitor
105 Views
Registered: ‎08-19-2019

回复: HOLDOVER clock for synchronous ethernet

Hi Simon,

thanks for you reply.

By the way  - a workaround is to switch the picxo itself to hold. But this is not the same like a solution with an external clock synchronizer chip and unfortunately we don't have it on board.

I thought I could find a DPLL with a NCO (dds compiler or so ..)  but there is no xapp about it. This one should provide a "hold" REFCLK based on locked CDR phase with external TCXO clock.

Thanks !!picxo.jpg

picxo.jpg
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Observer aforencich
Observer
52 Views
Registered: ‎08-14-2013

回复: HOLDOVER clock for synchronous ethernet

I think what you need to do is remove direct reference switching completely.  The PICXO works by adjusting the TX phase interpolator to tweak the frequency from the TX PLL.  The control loop in the PICXO attemps to force the TX clock of the transceiver into a specific relationship with the reference clock.  Placing PICXO in hold mode breaks the loop, essentially using the transceiver reference clock as a holdover oscillator. 

You have three options here, I think.

First, you could design the system so that the holdover oscillator itself is used as the transceiver reference clock, likely using an external PLL to convert it to the correct frequency.  Then simply place the PICXO in hold mode when the external source is not available.

Second, you could add another PLL of some sort to create a reference that's locked to the external source, based on the holdover oscillator.  This clock would then be used as the reference for the PICXO.  Placing this PLL in hold mode would "switch" to the holdover oscillator.  It might be possible to use an all-digital PLL or software PLL for this.

Third, you could use the holdover oscillator as the PICXO reference, then use a separate phase detector compare with the external reference and adjust the PICXO settings to lock the output frequency to the external reference.

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