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Adventurer
Adventurer
431 Views
Registered: ‎06-14-2018

Handle PL 10G link status

Hi all,

I have PL 10G working on ZCU102 based custom board, Vivado/Yocto 2019.1.

In Linux, the 10G interface is up & working. But It can't handle the status changes like fiber disconnected/connected, SFP+ module absent, host interface disabled(disable ethernet interface in PC)/enabled. I tested on 

Intel FTLX1471D3BCV-IT and FINISAR ftlx2072d327 + ftlx2072d333 pair.
 
So my question is, how can I make the Linux os handling 10G link status changes automatically? Thank you.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: Handle PL 10G link status

After the fiber disconnected and reconnected, can you do GTRXRESET one more time?

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Adventurer
Adventurer
365 Views
Registered: ‎06-14-2018

回复: Handle PL 10G link status

Hello @guozhenp ,

I think GTRXRESET is in FPGA? I'm not FPGA developer, so I have no idea about it :).

Anyway, can PL 10G FPGA IP detect the status changes? or PL 10G Linux driver can handle the status changes detection? Or I have to do it myself via SFP+ I2C command (SFF-8472 standard)?

Does Auto-Negotiation & Link Training feature in PL 10G IP relate to this?

Thank you.

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Visitor
Visitor
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Registered: ‎11-11-2019

回复: Handle PL 10G link status

Hi,

which 10G IP are you using?

For example the Xilinx 10G Ethernet Subsystem has a link status register, which you can read.

 

 

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Adventurer
Adventurer
287 Views
Registered: ‎06-14-2018

回复: Handle PL 10G link status

Hi @yubex and @guozhenp ,

Our FPGA design uses Xilinx 10G/25G Ethernet Subsystem, configuration as attached pictures.
I guess, due to BASE-R mode is used, so Auto-Negotiation & Link Training are disabled, so status registers are mostly empty. (10G IP has base address 0xa0050000):

~# devmem 0xA0050400
0x00000081
~# devmem 0xA0050460
0x00000000
~# devmem 0xA0050464
0x00000000
~# devmem 0xA0050468
0x00000000
~# devmem 0xA0050458
0x00000000
~# devmem 0xA0050400
0x00000080
~# devmem 0xA0050404
0x000000E0
~# devmem 0xA0050408
0x00000000
~# devmem 0xA005040c
0x00000001
~# devmem 0xA005043c
0x00000000
~# devmem 0xA0050448
0x00000000
~# devmem 0xA005044c
0x00000000
~# devmem 0xA0050450
0x00000000
~# devmem 0xA0050454
0x00000000
~# devmem 0xA0050458
0x00000000
~# devmem 0xA005045c
0x00000000
~# devmem 0xA0050460
0x00000000
~# devmem 0xA0050464
0x00000000
~# devmem 0xA0050468
0x00000000
~# devmem 0xA0050474
0x00000000
~# devmem 0xA0050498
0x00000001
~# devmem 0xA005049c
0x00000000
~# devmem 0xA0050500
0x00000000

I attached the boot log also. For now, the 10G interface doesn't work in U-boot, but it is not my target, so we can ignore u-boot in this topic.

For now, I use static IP on board's 10G interface, 10G PCI card on PC & static IP, PC & board connect directly via fiber cable & SFP+ modules. Everything works fine, except when I reset the 10G interface in PC (reboot the PC, turn off the PC's 10G interface then turn it on by "ifconfig" command) the connection between PC & board will be lost and I have to reset (ifconfig down then up) board's 10G interface to make it works again. That is my problem now.

Thank you for your time & any comments/ideas are appreciated.

 

 

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Adventurer
Adventurer
284 Views
Registered: ‎06-14-2018

回复: Handle PL 10G link status

Here are 10G configuration in FPGA & boot log. Thanks.

Screenshot from 2019-12-02 08-47-33.png

Screenshot from 2019-12-02 08-34-17.pngScreenshot from 2019-12-02 08-34-19.pngScreenshot from 2019-12-02 08-34-22.png

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Visitor
Visitor
253 Views
Registered: ‎11-11-2019

回复: Handle PL 10G link status

Hi,

according to PG210 page 233, the output "stat_rx_status" of the IP indicates the link status.

Can you use that output, to determine if you have a link or not?

 

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