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Registered: ‎04-26-2017

How can I see that gtrefclk is well configured?

Hello all,


I am trying to run the PCS/PMA IP Core, but I have some strange behaviours. For instance, in my simulation the userclk_out and  the userclk2_out have a good waveform and I can see their clocks, However, when I implement the design in my FPGA I don't receive any clock, so I am supposing that I have not configured correctly the gtrefclk.


To configure that clock I write these lines in my constraint file:

set_property PACKAGE_PIN C8 [get_ports mgt_clk_clk_p]
create_clock -period 8.000 -name mgt_clk [get_ports mgt_clk_clk_p]

Am I missing something? How can I check that the gtrefclk is well configured?


Thanks and best regards,



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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

回复: How can I see that gtrefclk is well configured?

1. You can open the post P&R result in Vivado and check the clock pins and the related nets connected correctly.

2. It can also be the HW issue, not the design. So you can also try IBERT test first.

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