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Observer
Observer
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Registered: ‎07-16-2017

How to use multi 1G/2.5G ethernet subsystems in single block design?

Hi,

The key issue is shared logic, I want to describe the problem in several cases.

1. Only one block uses include shared logic in core, the others include shared logic in example. as following:

1564991228(1).png

is this correct?is there any other timing issues? or some constraints issues? This design consist of 6 ethernet subsystems, or is there any suggestion in the distribution pin?

2.All blocks use include shared logic in core( Advice from some experts in this forum, another reason is that we use the us+ platform, so only IODELAY is shared logic.), but the problem is following:

微信图片_20190805170303.png

so I modified the xdc file as following:

微信截图_20190807122903.png

But the error message is changed to following:

微信图片_20190807113312.png 

I searched this issue in this forum, all solution indicated to the AR#64542, but this ar is about selectIO, not for multiple ethernet subsystems. (Although this problem is also due to internal selectIO)

For example:

微信图片_20190807124052.png

I can not find anything about this in my project.(the keyword IODELAY_GROUP)

So, how to solve this problem?

Thx a lot!

 

 

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