How to use multi ethernet subsystem in US+ design?
We need to use six 1G/2.5G Ethernet subsystems in our design. We used this design on the ZYNQ7k platform before, but when we designed on the us+ platform, we found that there is a big difference about the share logic between mpsoc and zynq7k.
Use multiple subsystems in zynq7k as shown below:(Select whether the IDELAYCTRL (and the Tx MMCM with its associated clock buffers for Artix-7 or Kintex-7 devices) are included in core or not included in core.)
But in us+ design, just IDELAYCTRL need to be shared, so the connection as below:
Is this correct?
If yes, finally we got this error at bitstream phase?