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Observer
Observer
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Registered: ‎07-16-2017

How to use multi ethernet subsystem in US+ design?

Hi,

We need to use six 1G/2.5G Ethernet subsystems in our design. We used this design on the ZYNQ7k platform before, but when we designed on the us+ platform, we found that there is a big difference about the share logic between mpsoc and zynq7k.

Use multiple subsystems in zynq7k as shown below:(Select whether the IDELAYCTRL (and the Tx MMCM with its associated clock buffers
for Artix-7 or Kintex-7 devices) are included in core or not included in core.)

1564991012(1).png

But in us+ design, just IDELAYCTRL  need to be shared, so the connection as below:

1564991228(1).png

Is this correct?

If yes, finally we got this error at bitstream phase?

微信截图_20190805155203.png

If not, How to use that?

Thx a lot!

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