03-03-2012 09:09 PM
GTX realizes physical layer of SATA protocol. Link layer and transport layers are implemented in VHDL with programmable logic resources. Application layer is developed on POWERPC440 embedded in Xilinx Virtex-5 FPGA. In order to test the performance of SATA controller PLB2SATAIP, an Embedded SATA Storage (ESS) reference system has been created in virtex 5 platform .The ESS reference system has been implemented in xilinx ML507 Evaluation Platform. The FPGA chip is XC5VFX70T.
The experiment results shows the maximal sustained sequential writes up to 215 MB/s and sustained sequential reads up to 273MB/s .( Intel Solid-State Drive 320 Series). The other was the utilization of the SATA controller is shown in table 1.
Slice Logic Utilization:
Number of Slice Registers: 2,902 out of 44,800 6%
Number used as Flip Flops: 2,902
Number of Slice LUTs: 3,097 out of 44,800 6%
Number used as logic: 2,815 out of 44,800 6%
Number using O6 output only: 2,475
Number using O5 output only: 184
Number using O5 and O6: 156
Number used as Memory: 251 out of 13,120 1%
Number used as Shift Register: 251
Number using O6 output only: 250
Number using O5 and O6: 1
Number used as exclusive route-thru: 31
Number of route-thrus: 219 out of 89,600 1%
Number using O6 output only: 215
Number using O5 output only: 4
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03-06-2012 12:50 AM
I want implement only link layer for my student project .
could you please help me by some document and source code.
I implement and test OOB correctly but don't know how start for link layer.
03-06-2012 02:31 AM