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Visitor zhanneta
Visitor
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Registered: ‎05-21-2019

IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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Hi,

 

I am working with CMAC 2.6 in Xilinx Vivado 2019.1 and have a question regarding IEEE 1588 timestamping.

 

In the user guide, it isn't clear where "reference fill level" is from. The following formula is illustrated in the user guide:

corrected_timestamp = rx_ptp_tstamp_out + (Reference Fill Level - rx_lane_aligner_fill_0)

 

I understood the following:

1. rx_ptp_tstamp_out is a timestamp of the start of packet that needs to be corrected based on lane aligner fills to get rid of clock cycle jitter

2. rx_ptp_pcslane_out is used to choose one of the rx_lane_aligner_fill_* (example: rx_ptp_pcslane_out = 3 -> use rx_lane_aligner_fill_3)

3. rx_ptp_pcslane_out is used to determine the physical lane using stat_rx_pcsl_number_* (example: rx_ptp_pcslane_out = 5 and stat_rx_pcsl_number_7 = 5 -> start of packet received on physical lane 7)

4. use physical lane number to find out the "reference fill level" -> HOW?

5. use the formula to calculate the corrected timestamp

 

Can you please correct me in my assumptions and help me understand how to get the "reference fill level"?

 

Thank you,

Zhanneta

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Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎05-01-2013

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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OK. Here're the details.

 

rx_lane_aligner_fill_0 is "rx_lane_aligner_fill_0"  for the lane on which the timestamp was taken.

Reference Fill Level is "rx_lane_aligner_fill_X". "X" here is for the lane on which SOP was detected (RX_PTP_PCSLANE_OUT) and is translated by stat_rx_pcsl_number_*.

 

For example, if RX_PTP_PCSLANE_OUT is 5, the customer should go to check stat_rx_pcsl_number_5 first. And if stat_rx_pcsl_number_5 is 15, he can use rx_lane_aligner_fill_15 as the reference fill level to minus rx_lane_aligner_fill_0 and compensate the timestamp.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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"Reference Fill Level" are CMAC outputs

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Visitor zhanneta
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Registered: ‎05-21-2019

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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I can't find "Reference Fill Level" among CMAC outputs. Can you please clarify?
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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Are you reading PG203? It lists as follows.

 

RX_LANE_ALIGNER_FILL_0[7-1:0]

O

RX_CLK

This output indicates the fill level of the alignment
buffer for PCS lane0. This information can be used
by the PTP application, together with the signal
RX_PTP_PCSLANE_OUT[4:0], to adjust for the lane
skew of the arriving SOP. The units are SerDes clock
cycles.

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Visitor zhanneta
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Registered: ‎05-21-2019

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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Yes, I am reading PG203. In the userguide, they share the following formula:

corrected_timestamp = rx_ptp_tstamp_out + (Reference Fill Level - rx_lane_aligner_fill_0)

From the description and the formula, it seems like "Reference Fill Level" and "rx_lane_aligner_fill_*" are not the same. In the userguide, they also say the following:

"The reference fill level is the average fill level of the rx lane aligner fill after the PCS lane number carried by rx_ptp_pcslane_out is translated to a PMD lane number via the stat_rx_pcsl_number_*."

It seems like you are supposed to translate RX_PTP_PCSLANE_OUT into physical lane number and then get the reference fill level somehow.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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OK. Here're the details.

 

rx_lane_aligner_fill_0 is "rx_lane_aligner_fill_0"  for the lane on which the timestamp was taken.

Reference Fill Level is "rx_lane_aligner_fill_X". "X" here is for the lane on which SOP was detected (RX_PTP_PCSLANE_OUT) and is translated by stat_rx_pcsl_number_*.

 

For example, if RX_PTP_PCSLANE_OUT is 5, the customer should go to check stat_rx_pcsl_number_5 first. And if stat_rx_pcsl_number_5 is 15, he can use rx_lane_aligner_fill_15 as the reference fill level to minus rx_lane_aligner_fill_0 and compensate the timestamp.

 

 

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Visitor zhanneta
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Registered: ‎05-21-2019

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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Thank you, that clarifies it!

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Visitor zhanneta
Visitor
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Registered: ‎05-21-2019

回复: IEEE 1588 Timestamping on CMAC: Clock Cycle Jitter Removal

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The problem is that in the datasheet these signals are defined as follows:

RX_PTP_PCSLANE_OUT = PCS lane where SOP was detected

STAT_RX_PCSL_NUMBER_X = indicates PCS lane received on physical lane X

RX_LANE_ALIGNER_FILL_X = indicates fill level of alignment buffer for PCS lane X

 

So, it doesn't make sense that we would have to translate RX_PTP_PCSLANE_OUT into physical lane because RX_LANE_ALIGNER_FILL_X is per PCS lane.

 

If what you are saying is true, the user guide has an error.

 

Should RX_LANE_ALIGNER_FILL_X be correspondant to physical lane (X = physical lane number)?

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