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4,185 Views
Registered: ‎09-19-2016

Issue with using XIlinx ethernet subsystem

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Hi,

 

   I am integrating TCP layer designed from comblock with 1/2.5G Ethernet subsystem for kintex 7 to design TCP client.On server side,same ethernet subsystem is repeated with TCP layer from comblock.This TCP layer from comblock is compatible with xilinx 6 and 7 series FPGAs as per their documentation.

   Now,we know for client server communication,3 way handshaking is mandatory to establish a link.When SYNC packet is sent from client to server as a first step of handshaking,the packet reaches to MAC layer of ethernet subsystem.Here transmit ready signal from MAC stays high for first 2 clk cycles and for next 8 clk cycles it stays at 0.Then it becomes '1'.I added some logic so that in those 8 clock cycles i wont send any data.When this packet comes out of gmii tx interface,error is induced in the packet at the last byte(8th byte) of preamble and this data is NOTgetting forwarded to serial interface(txn/txp ,which is on the transmit side of transceiver).The sync packet format is correct.

   

Below are the details and some observations :

 

     I am using axi_example_0_design as top level of client side and commented pattern generator block and axi fifo and included comblock tcp layer in it.Same module is replicated for server side.Both these modules are included in example design testbench.The configuration parameters in axi_lite_ctrl module in server side are changed(IP,physical ,port addresses are swapped).Init count1 in axi_lite_ctrl module is changed to F3h from 4FFh to speed up the simulation as resetdone becomes '1' before the counter ends.resetdone signal from pcs/pma goes high after approximately 3 ms.I am using same clocking structure as given in example design testbench.Phy is set to internal and sgmii interface is used between MAC and PHY at IP core settings in UI.

 

     During simulation,txresetfsm,rxresetfsm state machines in gtx transceiver runs fine after resetdone='1'.axi_lite_ctrl state machines work fine after MAC reset. Status_vector changes to 0806 after state machines(txresetfsm/rxresetfsm) in gtx_transceiver are in done state.Auto-negotiation is turned off on both client and server. rxnotintable goes '1' for few clk cycles after resetdone ='1',then it becomes '0'.

 

     What other things should I check ?Can you please help in this issue?

 

     

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Xilinx Employee
Xilinx Employee
7,758 Views
Registered: ‎02-06-2013

Re: Issue with using XIlinx ethernet subsystem

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Hi

 

I doubt that you are not driving the data after the tready is asserted again after the first two bytes which is causing frame error at Mac output.

 

Can you upload the simulation waveform for review.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
7,759 Views
Registered: ‎02-06-2013

Re: Issue with using XIlinx ethernet subsystem

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Hi

 

I doubt that you are not driving the data after the tready is asserted again after the first two bytes which is causing frame error at Mac output.

 

Can you upload the simulation waveform for review.

Regards,

Satish

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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4,087 Views
Registered: ‎09-19-2016

Re: Issue with using XIlinx ethernet subsystem

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Hi Sir,

 

      Thanks for your response.I ran the given example design testbench to see the tranaction happening on tx_mac_ready and valid signals.As you said,at second assertion of ready signal ,valid must be '1'.

 

      The issue is now resolved.

 

Cheers & Warm Regards,

Rohit

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