cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mc76
Newbie
Newbie
1,388 Views
Registered: ‎05-08-2018

JESD204B Data Latency

I've been reading about deterministic latency and subclass 1 and had a question about the latency when JESD enters the data phase:

I have an FPGA connected to a DAC and I only care about the latency after the JESD IP AXI stream TREADY is asserted to analog data out.

I don't mind the variable startup delay when releasing the buffer but I do need the delay between data in and data out during data phase to be the same power cycle to power cycle.

Do I need subclass 1? Should this be a concern? I feel like it's implied that the latency in the data phase is the same every time.

 

Thanks,

-mike

Tags (2)
0 Kudos
3 Replies
rpr
Moderator
Moderator
1,322 Views
Registered: ‎11-09-2017

Hi

Xilinx JESD can be configured to subclass 0, subclass 1 or subclass 2.

DAC you are looking for supports sub class 0 or sub class 1?

Supporting Subclass 1 deterministic latency requires to ensure that SYSREF (for Subclass 1)

For Subclass 0, where there are no such constraints.

 

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
0 Kudos
mc76
Newbie
Newbie
1,315 Views
Registered: ‎05-08-2018

Hi Pratap,

Thanks for your response.

My understanding is the subclass 1 provides deterministic latency from Power on Reset due to some variable delay in the ILAS stage.

My intention is to send 0s to the DAC until the FPGA decides it's ready to transfer a waveform (JESD should be well into the DATA phase). I'm wondering if the latency between when the FPGA decides to send and output changes between power cycles? If I synchronize multiple DACs by delaying samples in the FPGA, does this remain consistent through power cycles?

Thanks,

-mike

 

 

Capture.PNG
0 Kudos
shantmoses
Adventurer
Adventurer
1,296 Views
Registered: ‎07-01-2008

For multi DAC synchronization, ensure that all your DAC devices and the interface logic blocks (in single or multiple FPGAs) receive the same system reference clock and are configured to run in subclass 1 mode. The latency remains fixed and never changes between power cycles given that the end-to-end delay doesn't end up being too close to LMFC boundaries, otherwise an additional delay of 1 LMFC period can be introduced in the data path.

 

Regards,

Shant

0 Kudos