I have implemented a block design in Vivado 2018.1 for streaming the data to the Xilinx JESD204B IP. I am right now using a Kintex-7 FPGA which is to be interfaced with AD9172 DAC. As you can see from the block design, I am driving each and every peripheral along with Microblaze soft core processor with tx_core_clk_out and I have connected all the the resets to the tx_aresetn of the JESD204 IP and with only one external reset as shown in the design below. I have validated the design and it shows no errors. I am successful in generating the bit stream for my design. I am still wondering about the clock connections in the design. Also, I have SYNC and SYSREF as differential inputs which are coming from AD9172. I am using utility buffers to connect these differential inputs to the Xilinx JESD204P IP block. If anyone could check my design and let me know whether my design is OK or not it would be a great help.