09-03-2018 02:45 AM
I generated a JESD204B transmitter and a JESD204B phy separately with IP integrator. I'm using a ZCU102 with an Abaco FMC120 on HP0.
Taking a look at the JESD204B transmitter's register space (offset 0x04, as determined from the xparameters.h file and the IP Integrator address space), I see that the core is registering as being in reset.
tx_reset and tx_sys_reset are tied together, and are reset synchronous to core clock, after the CPLL's get their clocks. i'm adding a ILA monitor onto CPLLLOCk for all the transceivers and it is building now, but I wanted to ask:
Has anyone else dealt with this, and am I missing something?