UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer fehitrk
Observer
485 Views
Registered: ‎06-01-2018

KCU105 sgmii receive end packet loss

Jump to solution

Hi,

I am trying to use Xilinx SGMII interface to communicate through Ethernet interface of KCU105 board. I connected SGMII IP to a custom developed logic to handle RX packets and to generate TX packets.  The problem I have faced is:  I am receiving less number of packet than the one send from the other end. To check total received packets I am also checking the toggle number of RX_VLD and RX _ERR signals . As an example when other end send 250 packets, I receive roughly 190 packets (It is changing time to time). I am checking the send packets also Wireshark and it is correct. I also checked the received packet number through MARVELL PHY chip though MDIO interface (Page 12, Register 30). It is also correct.  Do you have an idea about the origin of this issue ? In the received packets, I have not faced with any errors.  I have not test whether transmit end has the similar problem.

Below are the SGMII IP (16.1) settings that I used in project:

--------------------------------

MDIO interface : Custom

Ethernet : Custom

MDIO : custom

----------------------------

Data Rate : 1G

Standard : SGMII

Physical Interface : LVDS serial

Enable Async SGMII : false

LVDS Reference Clk Freq: 625

Management options:

Only Auto negotiation is checked

SGMII PHY Mode is unchecked

Shared Logic : Include Shared Logic in Core is selected.

 

Thank you

 

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
453 Views
Registered: ‎11-09-2017

Re: KCU105 sgmii receive end packet loss

Jump to solution

Hi

 I understand that you are looking to interface xilinx SGMII with MAC (custom logic).

Xilinx SGMII Supports physical interfaces integrated device-specific transceiver interface/Low Voltage Differential Signaling
(LVDS).

Packets handling taken care by MAC, SGMII just transfers data (GMII to lane/IO).

Kindly monitor any statistic at MAC.

Generally FCS errors, Packets are shorter than 64 bytes, A frame does not match against any of the enabled frame filters can cause this issue.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
0 Kudos
2 Replies
Moderator
Moderator
454 Views
Registered: ‎11-09-2017

Re: KCU105 sgmii receive end packet loss

Jump to solution

Hi

 I understand that you are looking to interface xilinx SGMII with MAC (custom logic).

Xilinx SGMII Supports physical interfaces integrated device-specific transceiver interface/Low Voltage Differential Signaling
(LVDS).

Packets handling taken care by MAC, SGMII just transfers data (GMII to lane/IO).

Kindly monitor any statistic at MAC.

Generally FCS errors, Packets are shorter than 64 bytes, A frame does not match against any of the enabled frame filters can cause this issue.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
0 Kudos
Observer fehitrk
Observer
437 Views
Registered: ‎06-01-2018

Re: KCU105 sgmii receive end packet loss

Jump to solution

Hi,

Thank you for your reply. 

I found a bug in my custom design that interfacing with SGMII IP. The design was periodically triggering "an_restart_config" pin. After disabling that, I receive large number of packet without losing any of them.

 

Sincerely,

 

0 Kudos