11-14-2019 05:32 PM
Similar to an prior bug I found where the BSP does not correctly setup IRQ steering to CPUs[2,3] on the MPSoc; Our system uses a seperate application on each APU[0..3], each with LWiP and FreeRTOS, and each using a seperate GEM.
APU[0,1,2] all work after fixing the prior bug with the RTOS Tick IRQ not getting mapped from the GIC Target registers to CPU[2,3]. However CPU still would not process packets.
Tracing down the issue:
11-19-2019 05:56 AM
Hi @isaakian ,
Thank you for your post. When I read it, is it more of bug found and report issue for Xilinx? If so, would you be able to provide a test case so that I could reproduce the issue on my end? Have you tested with 2019.1/2 Vivado?
11-19-2019 12:39 PM
Yes, it's a bug report and solution both to help Xilinx and anyone else who runs into the same issue.
I have not tested on 2019.1/2 yet, but I looked at the latest driver (BSP) code from xSDK (2019.2) and I dont see any changes that would have fixed this.
To recreate bug:
1. Create a BSP project and asign it to CPU#3 (A53 APU core 3) and associate it with the GEM3 (TEMAC3)
2. Create a app project using that BSP, and create demo LWiP project TCP/IP Echo server.
This would show both IRQ bugs I believe.