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Visitor davekepley
Registered: ‎04-29-2016

Looking for some clarification on 10GBase-R Status bits 280-286,257

I am trying to understand what these bits represent.  

285:280 10GBASE-R PCS BER Counter TX clock source
286         Latched High RX high BER TX clock source
257  10GBASE-R PCS high BER TX clock source


I read in in PG068 that: "Too many Invalid Sync headers are received. This might or might not be reflected in the HIBER output status bit or MDIO register, depending on how many invalid sync headers are received."


So, how are these generated; what are they.  THese seem to occur on a pCS without lock and without a pattern gen/detect enabled.  Is this based on the idle sequences sent in the beginning?

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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: Looking for some clarification on 10GBase-R Status bits 280-286,257



The BASE-R 64B/66B PCS maps 64 bits of scrambled payload and 2 bits of unscrambled sync header into
66-bit encoded blocks. The 2-bit sync header allows establishment of 64B/66B block boundaries by the PCS
sync process. The sync header is 01 for data blocks and 10 for control blocks; the sync header is the only
position in the PCS block that always contain a transition and this feature of the code is used to establish
64B/66B block boundaries.


The Pcs block in the core looks at the sync header received from the line and asserts the status bits and this is independent of the block lock or pattern gen/det.


The idle also sent in the above mentioned format of 64+2


Refer IEEE 802.3 spec if you want more details.



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