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Observer vjyoth01
Observer
9,722 Views
Registered: ‎07-09-2012

ML507: Standalone Trimode Embedded Ethernet IP Core Problem

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I'm not able to get any of the example design of ethernet working to send and recieve packets bewteen PC and FPGA.

 

I've gone through numerous documentation but no luck yet. 

 

Here's what I do:

1: I'm using GMII interface; so set the jumper J22 & J23 to 1-2

2: I set the DIP SW6 at the back of the board to 00111010 to get 125MHz clock for Ethernet PHY

3. Setup the host pc network to 192.168.0.1 and subnet to 255.255.255.0

4. Generate IPcore using default options (Only EMAC0 selected) and import the example design files and program the FPGA using JTAG

----> No output, nothing happens, No Ethernet TX,RX led blink, No link established.

 

There's a folder in the Ipcore Directory called "Implement" --> Runnning the batch file causes it to generate a bit file(The sources that it uses is unknown, as there is no mention of the files it uses)

 

Programming that bit file cases a link to be established with PC saying 1GBPS link (With PC recieved packets 0 and only PC sent packets number increasing,and on board the ethernet RX LED doesn't light up). Also when I open wireshark, I can't see any packets coming from FPGA nor to FPGA.

 

Even the ARP table doesn't have entry of my FPGA.

 

My question is:

1: What am I doing wrong?

2: How do I know which IP my FPGA is using, is there way to find it out in generated core/example design?

3: Will the core use the MAC ID present on the sticker behind the board. or will it change with the core?

4. Why does the example design doesn;t not include the generated core. (I'm attaching the snapshot of the same) So, is the example design itself wrong?

5: How to send manual raw packets to the fpga?? Does anyone know a software or have a script for it? 

 

 

Thanks a lot for the help..:)

 

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Observer vjyoth01
Observer
10,213 Views
Registered: ‎07-09-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Sushant, thanks a ton for pointing in the right direction. Your UCF file gave me idea what exactly I was doing wrong. Finally I got the example design working. 

 

The problem is in the UCF file;  I made just a single change NET "GTX_CLK_0" LOC = "K18" ; and now its works like a charm.

And also, sometimes the ethernet come up on its own, we need to do reset after programmming the file(Sometimes); so I have to do a manual reset from the push button and the Ethernet MAC works as metioned in the document. 

 

Again thanks a lot... :) :) :)

 

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17 Replies
Xilinx Employee
Xilinx Employee
9,710 Views
Registered: ‎04-16-2008

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

When you generate the V5 Standalone Embedded TEMAC wrapper files the implementation script implements the example design included in the wrappers.  It does not specifically target the ML507 board though.

 

If you want a working design for that board you can see XAPP957:

http://www.xilinx.com/support/documentation/application_notes/xapp957.pdf

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Voyager
Voyager
9,696 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

I'm not able to get any of the example design of ethernet working to send and recieve packets bewteen PC and FPGA.

 

I've gone through numerous documentation but no luck yet. 

 

Here's what I do:

1: I'm using GMII interface; so set the jumper J22 & J23 to 1-2

2: I set the DIP SW6 at the back of the board to 00111010 to get 125MHz clock for Ethernet PHY

3. Setup the host pc network to 192.168.0.1 and subnet to 255.255.255.0

4. Generate IPcore using default options (Only EMAC0 selected) and import the example design files and program the FPGA using JTAG

----> No output, nothing happens, No Ethernet TX,RX led blink, No link established.

 


sushant:Provided jumper & DIP switch settings are correct according to ML507 user guide.

 

Are you sure you are getting the clock of 125Mhz inside FPGA,Can you please check this ?

 

Host pc ip address is set to "192.168.0.1" seems to be ok but Xilinx document recommends  to set it to 1.2.3.9.

You should follow the document for the first time to make the example design work lateron you can make customization in that.

 

Did you followed the steps given GMII design creation Manual(pdf file).

 

----> No output, nothing happens, No Ethernet TX,RX led blink, No link established.

 

Can you check your UCF file whether it is proper or not Are you sure about this ?

 

 

 

There's a folder in the Ipcore Directory called "Implement" --> Runnning the batch file causes it to generate a bit file(The sources that it uses is unknown, as there is no mention of the files it uses)

 

You have to check the script in detail.

Any how it will be picking up rtl from example directory only,If I am not wrong.

 

Programming that bit file cases a link to be established with PC saying 1GBPS link (With PC recieved packets 0 and only PC sent packets number increasing,and on board the ethernet RX LED doesn't light up). Also when I open wireshark, I can't see any packets coming from FPGA nor to FPGA.

 

above you are saying"----> No output, nothing happens, No Ethernet TX,RX led blink, No link established." Please Clarify and be sure about your issue.

 


Even the ARP table doesn't have entry of my FPGA.

 

My question is:

1: What am I doing wrong?

2: How do I know which IP my FPGA is using, is there way to find it out in generated core/example design?

3: Will the core use the MAC ID present on the sticker behind the board. or will it change with the core?

4. Why does the example design doesn;t not include the generated core. (I'm attaching the snapshot of the same) So, is the example design itself wrong?

5: How to send manual raw packets to the fpga?? Does anyone know a software or have a script for it? 

 

 

Thanks a lot for the help..:)

 


sushant: Did you try with the arp -s command ?

 

You have to assign the ip address to your board using your board's Physical/MAC address(the 1 which is printed on your board) eg:arp-s 1.2.3.5 00-0a-35-02-36-FF.

 

according to the screenshot I am not sure whther you are working on correct example design generated from coregen.

 

After assigning the ip address using  arp command to your board,you can try sending ping packets and see the response on wireshark.

 

Further if it doesnt work refer this document and you can fully debug the example design by inserting chipscope.

Observer vjyoth01
Observer
9,688 Views
Registered: ‎07-09-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

 Did you try with the arp -s command ?

 

You have to assign the ip address to your board using your board's Physical/MAC address(the 1 which is printed on your board) eg:arp-s 1.2.3.5 00-0a-35-02-36-FF.

 

according to the screenshot I am not sure whther you are working on correct example design generated from coregen.

 

After assigning the ip address using  arp command to your board,you can try sending ping packets and see the response on wireshark.

 

Further if it doesnt work refer this document and you can fully debug the example design by inserting chipscope.

 

 Thank you a lot for this document, the arp -s command works. But I followed the steps in the document, when I ping 1.2.3.5 (The IP of my FPGA) there only ICMP packets from PC from FPGA. None from FPGA to PC. They talk about modifying the UCF file for SGMII interface; what changes should we make for GMII interface. 

 

When I ping now, the RX LED blinks exactly the same number of times the ping command is issued. But till now, I've not been able to recieve a single packtet from FPGA.

 

The screen shot problem is fixed; the xilinx design example has a v5embedded mac wrapper vhdl file. So, the project manager uses that file and not the xco file. Removing that wrapper would solve that issue.

 



---> No output, nothing happens, No Ethernet TX,RX led blink, No link established

This problem occurs sometimes; with the example design imported into project and bit file generated, After programming, There is no link eshtablished and sometimes link gets established; with the same bit file. 


 

Are you sure you are getting the clock of 125Mhz inside FPGA,Can you please check this ?

 

Host pc ip address is set to "192.168.0.1" seems to be ok but Xilinx document recommends  to set it to 1.2.3.9.

You should follow the document for the first time to make the example design work lateron you can make customization in that.

 

Did you followed the steps given GMII design creation Manual(pdf file).

 

----> No output, nothing happens, No Ethernet TX,RX led blink, No link established.

 

Can you check your UCF file whether it is proper or not Are you sure about this ?

 

  

The switch settings are as per the document and the ucf has timing constraint on it. So, I think that 125Mhz clock is generated.  I read the document and made the necessary changes, but still no output. The example design itself doesn't work.

 

Yes I followed the manual, to generate the GMII interface.

I pasting the UCF file here, ( intially there was no RESET in the ucf file, then I added it )

 


UCF FILE

 

CONFIG PART = 5vfx70tff1136-1;

##################################
# BLOCK Level constraints
##################################

# EMAC0 Clocking
# EMAC0 TX Clock input from BUFG
NET "TX_CLK_0" TNM_NET = "clk_tx0";
TIMEGRP "v5emac_tx_clk0" = "clk_tx0";
TIMESPEC "TS_v5emac_tx_clk0" = PERIOD "v5emac_tx_clk0" 7700 ps HIGH 50 %;
# EMAC0 RX PHY Clock
NET "GMII_RX_CLK_0" TNM_NET = "phy_clk_rx0";
TIMEGRP "v5emac_clk_phy_rx0" = "phy_clk_rx0";
TIMESPEC "TS_v5emac_clk_phy_rx0" = PERIOD "v5emac_clk_phy_rx0" 7700 ps HIGH 50 %;

 

# Set the IDELAY values on the data inputs.
# Please modify to suit your design.
INST "*gmii0?ideldv" IDELAY_VALUE = 38;
INST "*gmii0?ideld0" IDELAY_VALUE = 38;
INST "*gmii0?ideld1" IDELAY_VALUE = 38;
INST "*gmii0?ideld2" IDELAY_VALUE = 38;
INST "*gmii0?ideld3" IDELAY_VALUE = 38;
INST "*gmii0?ideld4" IDELAY_VALUE = 38;
INST "*gmii0?ideld5" IDELAY_VALUE = 38;
INST "*gmii0?ideld6" IDELAY_VALUE = 38;
INST "*gmii0?ideld7" IDELAY_VALUE = 38;
INST "*gmii0?ideler" IDELAY_VALUE = 38;

INST "*gmii_rxc0_delay" IDELAY_VALUE = 0;

# GMII Receiver Constraints: place flip-flops in IOB
INST "*gmii0?RXD_TO_MAC*" IOB = true;
INST "*gmii0?RX_DV_TO_MAC" IOB = true;
INST "*gmii0?RX_ER_TO_MAC" IOB = true;

INST "*gmii0?GMII_TXD_?" IOB = true;
INST "*gmii0?GMII_TX_EN" IOB = true;
INST "*gmii0?GMII_TX_ER" IOB = true;

 

 

##################################
# LocalLink Level constraints
##################################


# EMAC0 LocalLink client FIFO constraints.

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_tran_frame_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_retran_frame_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_txfer_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_frame_in_fifo" TNM = "tx_fifo_wr_to_rd_0";


TIMESPEC "TS_tx_fifo_rd_to_wr_0" = FROM "tx_fifo_rd_to_wr_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_tx_fifo_wr_to_rd_0" = FROM "tx_fifo_wr_to_rd_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_tran_frame_tog" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_txfer_tog" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?frame_in_fifo" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog*" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable_0";

TIMESPEC "ts_tx_meta_protect_0" = FROM "tx_metastable_0" 5 ns DATAPATHONLY;

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*" TNM = "tx_addr_rd_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*" TNM = "tx_addr_wr_0";
TIMESPEC "TS_tx_fifo_addr_0" = FROM "tx_addr_rd_0" TO "tx_addr_wr_0" 10ns;

## RX Client FIFO
# Group the clock crossing signals into timing groups
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_store_frame_tog" TNM = "rx_fifo_wr_to_rd_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_addr_gray*" TNM = "rx_fifo_rd_to_wr_0";


TIMESPEC "TS_rx_fifo_wr_to_rd_0" = FROM "rx_fifo_wr_to_rd_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_rx_fifo_rd_to_wr_0" = FROM "rx_fifo_rd_to_wr_0" TO "v5emac_clk_phy_rx0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow for metastability settling time
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_store_frame_tog" TNM = "rx_metastable_0";

TIMESPEC "ts_rx_meta_protect_0" = FROM "rx_metastable_0" 5 ns;

 

##################################
# EXAMPLE DESIGN Level constraints
##################################

 

# GMII Logic Standard Constraints
INST "gmii_txd_0<?>" IOSTANDARD = LVTTL;
INST "gmii_tx_en_0" IOSTANDARD = LVTTL;
INST "gmii_tx_er_0" IOSTANDARD = LVTTL;

INST "gmii_rxd_0<?>" IOSTANDARD = LVTTL;
INST "gmii_rx_dv_0" IOSTANDARD = LVTTL;
INST "gmii_rx_er_0" IOSTANDARD = LVTTL;

INST "gmii_tx_clk_0" IOSTANDARD = LVTTL;
INST "gmii_rx_clk_0" IOSTANDARD = LVTTL;

# Keep clock inputs in global clock banks.
INST "gmii_rx_clk_0" LOC = "BANK4";

INST "GTX_CLK_0" IOSTANDARD = LVTTL;
INST "GTX_CLK_0" LOC = "BANK4";
INST "REFCLK" IOSTANDARD = LVTTL;
INST "REFCLK" LOC = "BANK4";

# Example placement for the GMII interface
INST "*dlyctrl0" LOC = "IDELAYCTRL_X1Y2";
INST "gmii_rxd_0<0>" LOC = "BANK4";
INST "gmii_rxd_0<1>" LOC = "BANK4";
INST "gmii_rxd_0<2>" LOC = "BANK4";
INST "gmii_rxd_0<3>" LOC = "BANK4";
INST "gmii_rxd_0<4>" LOC = "BANK4";
INST "gmii_rxd_0<5>" LOC = "BANK4";
INST "gmii_rxd_0<6>" LOC = "BANK4";
INST "gmii_rxd_0<7>" LOC = "BANK4";
INST "gmii_rx_dv_0" LOC = "BANK4";
INST "gmii_rx_er_0" LOC = "BANK4";


NET "RESET" LOC=E8

 

 

And Thanks a lot Sushant..

 



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Voyager
Voyager
9,684 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Thank you a lot for this document, the arp -s command works. But I followed the steps in the document, when I ping 1.2.3.5 (The IP of my FPGA) there only ICMP packets from PC from FPGA. None from FPGA to PC.

 


sushant:  What is the exact issue ? Whether there is issue for Transmission of packet from PC to FPGA or from FPGA to PC ? Please explain this clearly.

 


They talk about modifying the UCF file for SGMII interface; what changes should we make for GMII interface. 

 


sushant: Same changes you can do for GMII interface as well only you should neglect,if they talk anything specifc about GTP/GTX transceiver's as GMII is nothing to do with that.

 


When I ping now, the RX LED blinks exactly the same number of times the ping command is issued. But till now, I've not been able to recieve a single packtet from FPGA.

 


sushant:RX LED on board(fpga) blink means the board is able to receive packet from PC. DID TX LED blink ?

 

 


---> No output, nothing happens, No Ethernet TX,RX led blink, No link established

This problem occurs sometimes; with the example design imported into project and bit file generated, After programming, There is no link eshtablished and sometimes link gets established; with the same bit file.

 

 

 


sushant: Should not Happen,provided your UCF and clock is proper inside the design.

 

 


The switch settings are as per the document and the ucf has timing constraint on it. So, I think that 125Mhz clock is generated.  

 


Can you check this by operating a simpe circuit (eg a counter) on the clock of 125Mhz to make sure the clock is reaching inside the design and is working fine.

 


I read the document and made the necessary changes, but still no output. The example design itself doesn't work.

 


Like what changes you had done ? Pease explain.

 


Yes I followed the manual, to generate the GMII interface.

I pasting the UCF file here, ( intially there was no RESET in the ucf file, then I added it )

 

 


Regarding your UCF FIle.

 

UCF FILE

 

CONFIG PART = 5vfx70tff1136-1;

##################################
# BLOCK Level constraints
##################################

# EMAC0 Clocking
# EMAC0 TX Clock input from BUFG
NET "TX_CLK_0" TNM_NET = "clk_tx0";
TIMEGRP "v5emac_tx_clk0" = "clk_tx0";
TIMESPEC "TS_v5emac_tx_clk0" = PERIOD "v5emac_tx_clk0" 7700 ps HIGH 50 %;
# EMAC0 RX PHY Clock
NET "GMII_RX_CLK_0" TNM_NET = "phy_clk_rx0";
TIMEGRP "v5emac_clk_phy_rx0" = "phy_clk_rx0";
TIMESPEC "TS_v5emac_clk_phy_rx0" = PERIOD "v5emac_clk_phy_rx0" 7700 ps HIGH 50 %;

 

# Set the IDELAY values on the data inputs.
# Please modify to suit your design.
INST "*gmii0?ideldv" IDELAY_VALUE = 38;
INST "*gmii0?ideld0" IDELAY_VALUE = 38;
INST "*gmii0?ideld1" IDELAY_VALUE = 38;
INST "*gmii0?ideld2" IDELAY_VALUE = 38;
INST "*gmii0?ideld3" IDELAY_VALUE = 38;
INST "*gmii0?ideld4" IDELAY_VALUE = 38;
INST "*gmii0?ideld5" IDELAY_VALUE = 38;
INST "*gmii0?ideld6" IDELAY_VALUE = 38;
INST "*gmii0?ideld7" IDELAY_VALUE = 38;
INST "*gmii0?ideler" IDELAY_VALUE = 38;

INST "*gmii_rxc0_delay" IDELAY_VALUE = 0;

# GMII Receiver Constraints: place flip-flops in IOB
INST "*gmii0?RXD_TO_MAC*" IOB = true;
INST "*gmii0?RX_DV_TO_MAC" IOB = true;
INST "*gmii0?RX_ER_TO_MAC" IOB = true;

INST "*gmii0?GMII_TXD_?" IOB = true;
INST "*gmii0?GMII_TX_EN" IOB = true;
INST "*gmii0?GMII_TX_ER" IOB = true;

 

 

##################################
# LocalLink Level constraints
##################################


# EMAC0 LocalLink client FIFO constraints.

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_tran_frame_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_retran_frame_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_txfer_tog" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_frame_in_fifo" TNM = "tx_fifo_wr_to_rd_0";


TIMESPEC "TS_tx_fifo_rd_to_wr_0" = FROM "tx_fifo_rd_to_wr_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_tx_fifo_wr_to_rd_0" = FROM "tx_fifo_wr_to_rd_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_tran_frame_tog" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_txfer_tog" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?frame_in_fifo" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog*" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable_0";

TIMESPEC "ts_tx_meta_protect_0" = FROM "tx_metastable_0" 5 ns DATAPATHONLY;

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*" TNM = "tx_addr_rd_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*" TNM = "tx_addr_wr_0";
TIMESPEC "TS_tx_fifo_addr_0" = FROM "tx_addr_rd_0" TO "tx_addr_wr_0" 10ns;

## RX Client FIFO
# Group the clock crossing signals into timing groups
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_store_frame_tog" TNM = "rx_fifo_wr_to_rd_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_addr_gray*" TNM = "rx_fifo_rd_to_wr_0";


TIMESPEC "TS_rx_fifo_wr_to_rd_0" = FROM "rx_fifo_wr_to_rd_0" TO "v5emac_tx_clk0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_rx_fifo_rd_to_wr_0" = FROM "rx_fifo_rd_to_wr_0" TO "v5emac_clk_phy_rx0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow for metastability settling time
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_store_frame_tog" TNM = "rx_metastable_0";

TIMESPEC "ts_rx_meta_protect_0" = FROM "rx_metastable_0" 5 ns;

 

##################################
# EXAMPLE DESIGN Level constraints
##################################

 

# GMII Logic Standard Constraints
INST "gmii_txd_0<?>" IOSTANDARD = LVTTL;
INST "gmii_tx_en_0" IOSTANDARD = LVTTL;
INST "gmii_tx_er_0" IOSTANDARD = LVTTL;

INST "gmii_rxd_0<?>" IOSTANDARD = LVTTL;
INST "gmii_rx_dv_0" IOSTANDARD = LVTTL;
INST "gmii_rx_er_0" IOSTANDARD = LVTTL;

INST "gmii_tx_clk_0" IOSTANDARD = LVTTL;
INST "gmii_rx_clk_0" IOSTANDARD = LVTTL;

# Keep clock inputs in global clock banks.
INST "gmii_rx_clk_0" LOC = "BANK4";

INST "GTX_CLK_0" IOSTANDARD = LVTTL;
INST "GTX_CLK_0" LOC = "BANK4";
INST "REFCLK" IOSTANDARD = LVTTL;
INST "REFCLK" LOC = "BANK4";

# Example placement for the GMII interface
INST "*dlyctrl0" LOC = "IDELAYCTRL_X1Y2";
INST "gmii_rxd_0<0>" LOC = "BANK4";
INST "gmii_rxd_0<1>" LOC = "BANK4";
INST "gmii_rxd_0<2>" LOC = "BANK4";
INST "gmii_rxd_0<3>" LOC = "BANK4";
INST "gmii_rxd_0<4>" LOC = "BANK4";
INST "gmii_rxd_0<5>" LOC = "BANK4";
INST "gmii_rxd_0<6>" LOC = "BANK4";
INST "gmii_rxd_0<7>" LOC = "BANK4";
INST "gmii_rx_dv_0" LOC = "BANK4";
INST "gmii_rx_er_0" LOC = "BANK4";

NET "RESET" LOC=E8

 


Where are the GMII tx pins ?



 

Crap!

 

How it will work ? How the link will established ?

 

Your UCF File is not proper,you should not left it blank as "BANK4".

You should provide with the relevant PIN LOC's for GMII TXD/RXD pins in UCF file  to make the bit file work.

 

Tou can have a look at the schematic of your  board to get the PIN Loc's and assign it in UCF accordingly without any error.I hope it will work!

 

If still you get the issue in making the example design work,then try inserting chipscope to debug the example design.

 



Newbie breizh
Newbie
9,672 Views
Registered: ‎07-20-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Dears,

 

I got the same problem using GMII mode on the ML507 board.

 

I have generated to core with the folowing options:

- Enable EMAC 0

- Interface GMII

- Speed 1000Mbps (only)

- Tx flow control enable

- Rx flow control enable

 

I have imported the overall example files in my ise 13.4 project.

 

Then i have modify the top entity:

=> (entity) PHY_RESET : out std_logic;

=> (archi)  PHY_RESET <= not reset_i;

 

and the ucf file:

NET PHY_RESET LOC = "J14";
NET PHY_RESET IOSTANDARD = LVTTL;

 

The board jumpers for the 125MHz clock seems to be ok. However, the rx led show that my computer send

inrformations but the tx led is always off. Moreover WireShark show me that the board do not send information.

 

Can someone tell me if there are more modifications to perform on the VHDL/UCF file ?

I saw that many people have made it work but nobody have share a fully functionnal design :-)

 

Please help !

 

Thanks

 

Bertrand

 

 

 

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Observer vjyoth01
Observer
9,664 Views
Registered: ‎07-09-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Hi Sushant,

 

What is the exact issue ? Whether there is issue for Transmission of packet from PC to FPGA or from FPGA to PC ? Please explain this clearly.


The issue is that I'm unable to get the core working. If the design works properly as given in tutorials and manual, i can proceed to design with it.  The RX LED blinks, I thought FPGA is recieving some data. So, I connected the Block level Wrapper's RX data output (which is connected to the Local link FIFO) to the other set of LED's, but these LED's don't change at all even though the RX blinks, which means that there is no data actually coming  out of the EMAC wrapper.


Where are the GMII tx pins ?

 

Crap!

 

How it will work ? How the link will established ?

 

Your UCF File is not proper,you should not left it blank as "BANK4".

You should provide with the relevant PIN LOC's for GMII TXD/RXD pins in UCF file  to make the bit file work.

 

Tou can have a look at the schematic of your  board to get the PIN Loc's and assign it in UCF accordingly without any error.I hope it will work!

 

If still you get the issue in making the example design work,then try inserting chipscope to debug the example design.

 


This is the UCF flie genrated by the core. I tried with Xilinx 10.1, 12.2 and 14.1 version; they don't have connectivity to GMII TX or RX pins, In 12.2 and 14.1, the IP core UCF generates with 

"INST "gmii_rx_clk_0"     LOC = "H14"; 

This the the only major change in those version of IP core.

 

Also I looked through the general UCF file for the borad here:

http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf

 

But they don't have any GMII TX and RX pins; should we connect it to the PHY RX and TX pins??

 

If yes what are the necessary changes we should make for the design or the UCF file??

 

I've been spending so much time trying to get this working, but I'm not able to get anywhere near seeing the output. Please help me with this.. I would be really grateful to you.


Thank You.

 

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Voyager
Voyager
9,657 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

My dear friend,

 

Please read ug194 in detail.


 

The issue is that I'm unable to get the core working. If the design works properly as given in tutorials and manual, i can proceed to design with it.  The RX LED blinks, I thought FPGA is recieving some data. So, I connected the Block level Wrapper's RX data output (which is connected to the Local link FIFO) to the other set of LED's, but these LED's don't change at all even though the RX blinks, which means that there is no data actually coming  out of the EMAC wrapper.

 

 

This is the UCF flie genrated by the core. I tried with Xilinx 10.1, 12.2 and 14.1 version; they don't have connectivity to GMII TX or RX pins, In 12.2 and 14.1, the IP core UCF generates with 

"INST "gmii_rx_clk_0"     LOC = "H14"; 

This the the only major change in those version of IP core.

 

Also I looked through the general UCF file for the borad here:

http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf

 

But they don't have any GMII TX and RX pins; should we connect it to the PHY RX and TX pins??

 

If yes what are the necessary changes we should make for the design or the UCF file??

 

I've been spending so much time trying to get this working, but I'm not able to get anywhere near seeing the output. Please help me with this.. I would be really grateful to you.


 

 


sushant: Please update your exsisting ucf generated by the core which you are  going to use in your design.

                 Remember don't confuse/misunserstand with the name PHY_TXD/RXD,RXDV<ER...etc,

                 These are the actual signals going to communicate with PHY device.You have to replace this with gmii

                 pins/ports present in your top-level hdl wrapper file.

 

 

                        i hope you understand!

 

NET  PHY_COL              LOC="B32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_CRS              LOC="E34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_INT              LOC="H20";   # Bank 3, Vcco=2.5V, No DCI      
NET  PHY_MDC              LOC="H19";   # Bank 3, Vcco=2.5V, No DCI      
NET  PHY_MDIO             LOC="H13";   # Bank 3, Vcco=2.5V, No DCI      
NET  PHY_RESET            LOC="J14";   # Bank 3, Vcco=2.5V, No DCI      
NET  PHY_RXCLK            LOC="H17";   # Bank 3, Vcco=2.5V, No DCI      
NET  PHY_RXCTL_RXDV       LOC="E32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_RXD0             LOC="A33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_RXD1             LOC="B33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_RXD2             LOC="C33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  PHY_RXD3             LOC="C32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_RXD4             LOC="D32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_RXD5             LOC="C34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_RXD6             LOC="D34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_RXD7             LOC="F33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_RXER             LOC="E33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  PHY_TXC_GTXCLK       LOC="J16";   # Bank 3, Vcco=2.5V, No DCI
NET  PHY_TXCLK            LOC="K17";   # Bank 3, Vcco=2.5V, No DCI
NET  PHY_TXCTL_TXEN       LOC="AJ10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD0             LOC="AF11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD1             LOC="AE11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD2             LOC="AH9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD3             LOC="AH10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD4             LOC="AG8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD5             LOC="AH8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD6             LOC="AG10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  PHY_TXD7             LOC="AG11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  PHY_TXER             LOC="AJ9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors    

Voyager
Voyager
9,652 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Bertrand wrote:

 

Dears,

 

I got the same problem using GMII mode on the ML507 board.

 

I have generated to core with the folowing options:

- Enable EMAC 0

- Interface GMII

- Speed 1000Mbps (only)

- Tx flow control enable

- Rx flow control enable

 

I have imported the overall example files in my ise 13.4 project.

 

Then i have modify the top entity:

=> (entity) PHY_RESET : out std_logic;

=> (archi)  PHY_RESET <= not reset_i;

 

and the ucf file:

NET PHY_RESET LOC = "J14";
NET PHY_RESET IOSTANDARD = LVTTL;

 

The board jumpers for the 125MHz clock seems to be ok. However, the rx led show that my computer send

inrformations but the tx led is always off. Moreover WireShark show me that the board do not send information.

 


sushant: If the link is successfully established @1gbps provided the UCF/hdl files are properly updated according to the reference manual.

 

Can you check whether the ping packet reaches the MAC or not ?

 

Can you try inserting chipscope into the design to debug this ?

 


Can someone tell me if there are more modifications to perform on the VHDL/UCF file ?

I saw that many people have made it work but nobody have share a fully functionnal design :-)

 

 

Please help !

 

Thanks

 

Bertrand

 


sushant: Please update your UCF file with (GMII txd & rxd pins) generated with the core and try inserting chipscope.

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Observer vjyoth01
Observer
9,645 Views
Registered: ‎07-09-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

sushant: Please update your exsisting ucf generated by the core which you are  going to use in your design.

                 Remember don't confuse/misunserstand with the name PHY_TXD/RXD,RXDV<ER...etc,

                 These are the actual signals going to communicate with PHY device.You have to replace this with gmii

                 pins/ports present in your top-level hdl wrapper file.

 

 

                        i hope you understand!


Thank You sushant, I understand now.. I modified the UCF file for the RXD and TXD pins. But no improvement at all. When I ping, RX leds blinks but TX doesn't.  Also, I connected the RXD data lines from GMII to GPIO LED's, but I see no change in LED status, although the RX LED blinks.

 

What does this mean?? If the RX blinks indicating that it is recieving some data, why don't the RXD Data line LED's change?? It shouldn't happen like this right??

 


Inserting a chipscope

 

I get a warning message: Upload command failed - No new data

 

I conncected the REFCLK, GTX_CLK and RX_CLK and tried to debug, but the same happens .

Re-installed USB drivers and complete Xilinx but same thing happens

 

Do you have a working ethernet ISE project for ML507?have u been able to get the standalone ethernet to work on ML507?

I found in another forum, the design works fine for ML505 but not for ML507?

 

If you have a workig ehternet ISE project for ML507 , can you send it?



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Voyager
Voyager
8,538 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Thank You sushant, I understand now.. I modified the UCF file for the RXD and TXD pins. But no improvement at all. When I ping, RX leds blinks but TX doesn't.  Also, I connected the RXD data lines from GMII to GPIO LED's, but I see no change in LED status, although the RX LED blinks.

 

What does this mean?? If the RX blinks indicating that it is recieving some data, why don't the RXD Data line LED's change?? It shouldn't happen like this right??

 


sushant: I can't comment on this as I had not tried taking RX/TX data on GPIO LED's.

 


I get a warning message: Upload command failed - No new data

 

I conncected the REFCLK, GTX_CLK and RX_CLK and tried to debug, but the same happens .

Re-installed USB drivers and complete Xilinx but same thing happens

 


sushant: Please refer attach Answer record to insert Chipsope in your design,I hope it would be helpful.

 


Do you have a working ethernet ISE project for ML507?have u been able to get the standalone ethernet to work on ML507?


sushant: yes!


I found in another forum, the design works fine for ML505 but not for ML507?


sushant: Don't Worry! It will work! Have Patience!

 


 


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Voyager
Voyager
8,527 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Vinayaka Jyoti wrote:

I'm unable to understand, where the error is. I have gone through the
documents; also regarding the chipscope, I guess the clock is not
getting genererated. As you said, I tried to drive a counter using the
clock and display it on GPIO LED's, but nothing changed.


sushant:

 

Yes it is very much forthright that the clock of 125Mz which is required to drive the design is not working inside your design.

 


So, is it problem with the Clock. If this is the case, what am I doing wrong?


Claptrap!

 

your UCF doesn't contain the constraints required. How the 125Mhz clock will work inside the design?

 

Use the attach UCF with your project and check the counter again.

 

Let  me know the feedback!


Observer vjyoth01
Observer
10,214 Views
Registered: ‎07-09-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Sushant, thanks a ton for pointing in the right direction. Your UCF file gave me idea what exactly I was doing wrong. Finally I got the example design working. 

 

The problem is in the UCF file;  I made just a single change NET "GTX_CLK_0" LOC = "K18" ; and now its works like a charm.

And also, sometimes the ethernet come up on its own, we need to do reset after programmming the file(Sometimes); so I have to do a manual reset from the push button and the Ethernet MAC works as metioned in the document. 

 

Again thanks a lot... :) :) :)

 

View solution in original post

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Voyager
Voyager
8,511 Views
Registered: ‎04-02-2011

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Glad to hear from you that you made it working.

 

Happy Designing!

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Visitor pranalishah
Visitor
8,504 Views
Registered: ‎07-10-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

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Nice thread,It helped me to get the example design work for V5 EMAC.

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Newbie woshivbn258
Newbie
8,399 Views
Registered: ‎09-18-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

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hello! I have a special problem in SGMII ethernet .when I send 10000 frames from FPGA to PC, it will miss almost 500 frames,and the length of one frame is 1500bytes. I have no idea about it,before i have tried so much,but it yet lost the frames. choud you give me some assistance? thanks a lot.

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Visitor tomkan
Visitor
8,268 Views
Registered: ‎10-24-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

Jump to solution

Hi

 

I got the problem using GMII mode on the ML507 board.FPGA(XC5VLX110T_FF1136_ -1)

I use ISE13.4.

 

Could you please help me to resolve some  question:

 

1.

Which IP does you choice in IP CORE GENERATOR:
(1):Virtex-5 Embedded TRI-Mode Ethernet MAC Wrapper. (Version:1.8)

(2): Tri Mode Ethernet MAC (Version:4.5)

 

2.

Could you please post your UCF file to me,because I met a big problem about pin assignment.

 

Thank you very much.

 

 

Tom

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Visitor md_alea
Visitor
8,179 Views
Registered: ‎10-28-2012

Re: ML507: Standalone Trimode Embedded Ethernet IP Core Problem

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Could somebody help us here? I kinda have the same problem. I followed all the steps discussed here, but still I can't get even the LEDs turning on. Thanks in advance.

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