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Registered: ‎10-10-2007

Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

I'm using the XUPV2P board with the 512MB Dual Rank DDR.  So, needed to modify the Slideshow example project from 256MB DDR to 512 Dual Rank DDR.  I’ve kept the configuration using the opb2dcr bridge.  I’ve managed to display a small color bitmap image of 32x32 pixels but I’m not able to display larger images (i.e. the images given in the example).  I’ve managed to narrow the problem to the sysace_fread() function.  

 


/*snip*/

    for (j=infoheader.height-1;j>=0;j--) {

      numread = sysace_fread(readBuffer, 1, 1920, infile);

      for (i=0;i<infoheader.width;i++) {

            temp = ((((readBuffer[i*3+2] << 8) | readBuffer[(i*3)+1]) << 8) | readBuffer[(i*3)]);

            writeaddr = baseaddr+(j*4096)+(i*4);

            XIo_Out32(writeaddr, temp);

      }

    }

/*snip*/

 

This function, I believe is supposed to read one line of the bitmap at a time.  Each line is store in a temporary location.  Later, pixel encoding is applied and then sent to DDR.  The problem is that it only iterates through each line (j) about 17 times then hangs.  I was guessing that the heap space wasn’t large enough, so I increased it and the stack to 0x1000.  Still it hangs.

 

I’m using EDK and ISE 9.1.  Any ideas?

Chandra

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 9.1.02 Build EDK_J_SP2.4
# Wed Oct 10 10:22:31 2007
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:     virtex2p
# Device:     xc2vp30
# Package:     ff896
# Speed Grade:     -7
# Processor: PPC 405
# Processor clock frequency: 100.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory :  64 KB
# Total Off Chip Memory : 512 MB
# - DDR_SDRAM_64Mx64 Dual Rank = 256 MB
# - DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 = 256 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = IO
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn, DIR = O
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn, DIR = O
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn, DIR = O
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn, DIR = O, VEC = [0:1]
 PORT fpga_0_net_gnd_pin = net_gnd, DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_CLK_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_CLK, DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC, DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC, DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK, DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_B_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_B, VEC = [5:0], DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_G_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_G, VEC = [5:0], DIR = O
 PORT fpga_0_VGA_FrameBuffer_TFT_LCD_R_pin = fpga_0_VGA_FrameBuffer_TFT_LCD_R, VEC = [5:0], DIR = O
 PORT fpga_0_Audio_Codec_Bit_Clk_pin = fpga_0_Audio_Codec_Bit_Clk, DIR = I
 PORT fpga_0_Audio_Codec_AC97Reset_n_pin = fpga_0_Audio_Codec_AC97Reset_n, DIR = O
 PORT fpga_0_Audio_Codec_SData_In_pin = fpga_0_Audio_Codec_SData_In, DIR = I
 PORT fpga_0_Audio_Codec_SData_Out_pin = fpga_0_Audio_Codec_SData_Out, DIR = O
 PORT fpga_0_Audio_Codec_Sync_pin = fpga_0_Audio_Codec_Sync, DIR = O
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc405
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT CPMC405CLOCK = sys_clk_s
END

BEGIN ppc405
 PARAMETER INSTANCE = ppc405_1
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_1
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
 BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_OPBCLK_PLB2OPB_REARB = 100
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_PROC_INTRFCE = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 2
 PARAMETER C_RNG0_BASEADDR = 0xD0000000
 PARAMETER C_RNG0_HIGHADDR = 0xD0000FFF
 PARAMETER C_RNG1_BASEADDR = 0x78000000
 PARAMETER C_RNG1_HIGHADDR = 0x7807FFFF
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
 PORT PLB_Clk = sys_clk_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x78050000
 PARAMETER C_HIGHADDR = 0x7805FFFF
 BUS_INTERFACE SOPB = opb
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x78060000
 PARAMETER C_HIGHADDR = 0x7806ffff
 BUS_INTERFACE SOPB = opb
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_gpio
 PARAMETER INSTANCE = PushButtons_5Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x78040000
 PARAMETER C_HIGHADDR = 0x7804ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
END

BEGIN plb_ddr
 PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 2
 PARAMETER C_NUM_CLK_PAIRS = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
 PARAMETER C_MEM1_BASEADDR = 0x10000000
 PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
 PARAMETER C_ECC_DEFAULT_ON = 0
 PARAMETER C_ENABLE_ECC_REG = 0
 BUS_INTERFACE SPLB = plb
 PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT PLB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_ac97
 PARAMETER INSTANCE = Audio_Codec
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x78030000
 PARAMETER C_HIGHADDR = 0x7803ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT Bit_Clk = fpga_0_Audio_Codec_Bit_Clk
 PORT SData_In = fpga_0_Audio_Codec_SData_In
 PORT SData_Out = fpga_0_Audio_Codec_SData_Out
 PORT Sync = fpga_0_Audio_Codec_Sync
 PORT AC97Reset_n = fpga_0_Audio_Codec_AC97Reset_n
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_include_burst_cacheln_support = 1
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xffff0000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLK180_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLK180 = sysclk_inv
 PORT CLK270 = clk90_inv
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 60
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK270 = ddr_clk90_inv
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

BEGIN opb2dcr_bridge
 PARAMETER INSTANCE = opb2dcr_bridge_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xD0000000
 PARAMETER C_HIGHADDR = 0xD00003FF
 BUS_INTERFACE SOPB = opb
 BUS_INTERFACE MDCR = dcr_v29_0
END

BEGIN plb_tft_cntlr_ref
 PARAMETER INSTANCE = VGA_FrameBuffer
 PARAMETER HW_VER = 1.00.d
# PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0b00000111111
 PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0b00000000000
 PARAMETER C_PIXCLK_IS_BUSCLK_DIVBY4 = 0b1
 PARAMETER C_ON_INIT = 0b0
# start with display off
 PARAMETER C_DCR_BASEADDR = 0b0000010000
 PARAMETER C_DCR_HIGHADDR = 0b0000010001
 BUS_INTERFACE MPLB = plb
 BUS_INTERFACE SDCR = dcr_v29_0
 PORT SYS_dcrClk = sys_clk_s
 PORT TFT_LCD_CLK = fpga_0_VGA_FrameBuffer_TFT_LCD_CLK
 PORT TFT_LCD_HSYNC = fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC
 PORT TFT_LCD_VSYNC = fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC
 PORT TFT_LCD_B = fpga_0_VGA_FrameBuffer_TFT_LCD_B
 PORT TFT_LCD_G = fpga_0_VGA_FrameBuffer_TFT_LCD_G
 PORT TFT_LCD_R = fpga_0_VGA_FrameBuffer_TFT_LCD_R
 PORT TFT_LCD_BLNK = fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK
END

BEGIN dcr_v29
 PARAMETER INSTANCE = dcr_v29_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_DCR_NUM_SLAVES = 1
END



MSS File

PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = ppc405_0
 PARAMETER STDIN = RS232_Uart_1
 PARAMETER STDOUT = RS232_Uart_1
END

BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = ppc405_1
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu_ppc405
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ppc405_0
 PARAMETER COMPILER = powerpc-eabi-gcc
 PARAMETER ARCHIVER = powerpc-eabi-ar
 PARAMETER CORE_CLOCK_FREQ_HZ = 100000000
END

BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu_ppc405
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ppc405_1
 PARAMETER COMPILER = powerpc-eabi-gcc
 PARAMETER ARCHIVER = powerpc-eabi-ar
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = plbarb
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = plb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = jtagppc_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = reset_block
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = plb2opb
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = plb2opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = RS232_Uart_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sysace
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = SysACE_CompactFlash
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = PushButtons_5Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tft_ref
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = VGA_FrameBuffer
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ac97
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = Audio_Codec
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1_bram
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = sysclk_inv
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = clk90_inv
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ddr_clk90_inv
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = opb2dcr_bridge_0
END


BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = xilfatfs
 PARAMETER LIBRARY_VER = 1.00.a
 PARAMETER PROC_INSTANCE = ppc405_0
 PARAMETER CONFIG_MAXFILES = 15
END

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14 Replies
Visitor jatxl3
Visitor
19,629 Views
Registered: ‎09-11-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

why not go on increase the stack and heap size,  like 0x8000, if your memory is large enough
 
also suggesting try 800x600 image first,
 
we have successfully implement the 800x600 bmp slideshow
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19,599 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

I've tried increasing the the plb_bram to 128K and increasing the stack and heap to 0xb000.  I can read 100x100 pixel 24-color bitmaps but not 105x105.  Are you using the 512MB Dual Rank memory?  Can I see your configuration files and your linker script?  I beginning to think that this isn't solely the heap and stack being too small.

Thanks in advance.
Chandra
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Newbie gorisdean
Newbie
19,570 Views
Registered: ‎10-17-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Hello,
 
Can anyone tell me where to find the necesarry files for this example project.
I've been searching thi Xilinx Website, but can't find the right download page.
 
Thanks
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19,558 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

http://www.xilinx.com/univ/xupv2p.html

or

http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P

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Newbie sjimit
Newbie
19,207 Views
Registered: ‎01-15-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Have you got this problem solved? I am also stuck in reading files from flash drive, which worked initially. Now it has stopped worked suddenly.



Message Edited by sjimit on 01-15-2008 11:07 AM
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19,196 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

No. Still haven't been able to use larger images stored on the compact flash.  A colleague and I are working to dump images from the serial port for now.  He's managed to determine that large files are causing a system reset.  And apparently, images that are taller than 480 pixels causes problems with the framebuffer.

That's all we know so far.
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Visitor pyter
Visitor
19,179 Views
Registered: ‎01-15-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Hi there.

I've already worked with a Spartan3 (using only pure VHDL) and now I'm working with a Virtex II PRO with Microblaze.

I've already did some small projects like using RS232 to show some stuff on the Hyperterminal, and using PS/2 to read from a keyboard...
Now I want to try out something like the Slideshow Project, but I'm completly lost...

First thing I would like to do is to show only a one color bitmap on the screen...
I've always used the BSB Wizard, but the VGA support is not there... or maybe it is, but I'm completly noob...

I did a similar project for the Spartan3 but with VHDL only (not using Microblaze). I want to know how do I do it on Virtex II PRO using Microblaze...


I tryed to open the Slideshow Project but it was created with an older version of EDK (I have 9.1.02i) and when converting it gives me the following errors:



ERROR:MDT - IPNAME:opb_ac97 HW_VER:2.00.a - Can not find valid MPD
ERROR:MDT - IPNAME:opb_ac97 HW_VER:2.00.a - Can not find valid MPD
ERROR:MDT - C:\pyter\EDK\slideshow_256mb\system.mss line 86 - Can not find MDD for the driver ac97 2.00.a
ERROR:MDT - Can not find MDD for the driver ac97 2.00.a
ERROR:MDT - IPNAME:opb_ac97 HW_VER:2.00.a - Can not find valid MPD
ERROR:MDT - IPNAME:opb_ac97 HW_VER:2.00.a - Can not find valid MPD
ERROR:MDT - C:\pyter\EDK\slideshow_256mb\system.mss line 86 - Can not find MDD for the driver ac97 2.00.a
ERROR:MDT - Can not find MDD for the driver ac97 2.00.a





Appreciate any help you can give to me...

Thanks.



EDIT: I found the driver (tft_ref_v1_00_a)... but how can I add it as an IP? And what about the connections?... Help!...




Message Edited by pyter on 01-17-2008 11:24 AM
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19,152 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

The tft_ref_v1_00_a is the software driver.  I believe this is found in the EDK XUP-V2Pro pack provided by Digilent in the drivers folder.  You also need the plb_tft_cntlr_ref_v1_00_d found in the pcores directory also provided in the same pack.

If I remember correctly, the easiest way to include the plb_tft in your project is to copy over the plb_tft_cntlr_ref_v1_00_d into the pcores directory in your project and similarly copy the tft_ref_v1_00_a into your project's drivers directory.  When you open your project, you should see the plb_tft_cntlr_ref in your ip catalog.  At this point you can add it like you would any other ip.  Just make sure that you set your parameters correctly.

Here is a reference that could help.  Also look at the mhs parameter info from the slideshow example and from the ddr_vga examples.
http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=74&query.id=13489#M74

As far as the errors you've received, I'm guessing that you didn't upgrade the ip for the opb_ac97.  No worries.  I deleted anything related to the opb_ac97 and the pushbuttons from my project and eventually got it to work.  I don't know for sure, but I don't believe this was necessary for the project to work...somewhat.

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Visitor pyter
Visitor
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Registered: ‎01-15-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Thanks for the answer!

There's no need to add the tft_ref driver to pcores folder, the plb_tft_ctrl_ref_v1_00_d is already on the IP Catalog.

Either way I'm still stuck... I'm kinda following a tutorial for PPC from James Lucero:

http://www.eece.unm.edu/xup/docs/IP_EDK_Integration_part2.pdf

But I don't know if I need the DCR Bus or not since TFT seems to use the PLB Bus and the only thing I would need is this bus and a PLB2OPB Bridge...


This is what I made so far:

1. Create a BSB Project only with the RS232 Peripheral (UARTLite)
2. Add a PLB Bus
3. Add a PLB2OPB Bridge
4. Add the plb_tft_ctrl_ref IP
5. Set PLB2OPB Bridge PLB Connection as Slave and OPB as Master
6. Set plb_tft_ctrl PLB Connection as Master
7. Set dcm_0 CLKDV Port as True and the CLKDV Divisor as 8.0
8. Set CLKDV Net Name as "tft_clk"
9. On plb_tft_ctrl_ref set SYS_tftClk as "tft_clk" and the rest as their "default" names (TFT_LCD_HSYNC as plb_tft_ctrl_ref_0_TFT_LCD_HSYNC, etc...) and make them all (except SYS_tftClk) as External Ports

And now I'm stuck... And I got this when I try to Generate Bitstream:



Performing System level DRCs on properties...

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING: plb_v34_0 DCR bus interface is not set
WARNING: plb2opb_bridge_0 DCR bus interface is not set

Check platform configuration ...
IPNAME:opb_v20 INSTANCE:mb_opb - C:\Semeano\EDK\vga3\system.mhs line 59 - 3
master(s) : 1 slave(s)
IPNAME:lmb_v10 INSTANCE:ilmb - C:\Semeano\EDK\vga3\system.mhs line 83 - 1
master(s) : 1 slave(s)
IPNAME:lmb_v10 INSTANCE:dlmb - C:\Semeano\EDK\vga3\system.mhs line 91 - 1
master(s) : 1 slave(s)
IPNAME:plb_v34 INSTANCE:plb_v34_0 - C:\Semeano\EDK\vga3\system.mhs line 173 - 1
master(s) : 1 slave(s)

Check port drivers...
ERROR:MDT - INST:plb_v34_0 PORT:PLB_Clk CONNECTOR:plb_v34_0_PLB_Clk -
   C:\Semeano\EDK\vga3\system.mhs line 176 - No driver found!
WARNING:MDT - INST:dcm_0 PORT:LOCKED CONNECTOR:dcm_0_lock -
   C:\Semeano\EDK\vga3\system.mhs line 153 - floating connection!

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ERROR:MDT - platgen failed with errors!




Help...
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10,414 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

I haven't seen the tutorial that you've mentioned.

But, I noticed you are missing something from your project.  You need to add the opb2dcr_bridge.  The opb will be slave and the dcr will be master. The project will automatically include the dcr_v29 (in my case).

As far as ports for the plb_tft_cntlr, I don't have a signal connected to tft_clk.  I have SYS_plbclk and SYS_dcrclk connected to the sys_clk_s.  I can't tell you if the clock configuration you've chosen will work or not.

I don't have enough information to help you resolve your errors.
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Visitor pyter
Visitor
10,409 Views
Registered: ‎01-15-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

I'm sorry to bother you but I'm doing the first steps on Virtex and Microblaze and I really have a lot to learn...

So, I added the tft_ctrl, the PLB bus, the DCR bus, the PLB2OPB bridge and the OPB2DCR bridge.
Then I set PLB_Clk as sys_clk_s and SYS_rst as sys_rst_s, and this is what I get so far:

The Bus Interface:

(a square means Master connection and a circle Slave connection)


The Ports:




And finally the Addresses:




Now, how do I connect all this stuff (PLB, DCR, TFT, bridges, etc.) in order to generate the bitstream with no errors and to go the next step (C programming)?

Thanks a lot.


Message Edited by pyter on 02-27-2008 07:25 AM
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10,386 Views
Registered: ‎10-10-2007

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

I've never used Microblaze, so I'm not familiar with the MB bus connections.

You have no ports connected to your plb_tft_cntlr_ref.  And all of your available ports are not showing.  So first you need to go to Connection Filters and select All.  Then check to see that your clocks are set as I described them before.  All of your main clocks for the buses should be the same. Then you need to connect your Vsync, Hsync, R,G,B, and BLNK ports for the tft.  There should be signals similiar to plb_tft_cntlr_ref_Vsync.

In your addresses, you need to set your plb_tft_cntlr_ref to 2 bytes.  I think the default address should be ok.  Then you need to set the size of your opb2dcr address size (mine is set at 1k) and location (default should be ok).  And I have a second address range for the plb2opb that encompasses the address space for the opb2dcr.  This is found in the mhs file in the slideshow example.  But again, it uses the PPC and not the MB. 

Remember to follow your signals.  Make sure you know where each is going and there purpose.
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Visitor pyter
Visitor
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Registered: ‎01-15-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Back again...

Ok, I think I have the hardware settings all done. I have it like this:

Ports:



Addresses:




Then I created a new project, added the libraries to Compiler Options, and did the following:


#include <xparameters.h>
#include "xio.h"
#include "xtft.h"

#define BaseAddress 0b1000000000;


int main(void){

    unsigned int xtft =
BaseAddress;

    XIo_Out32(0xD0000044, 0x1);  // turn on display

    XTft_SetPixel(xtft, 10, 10, 0xffffffff);

    return 0;
}



And guess what!... Blank screen.......

I think something must be wrong in the connections because I'm having warnings about floating connections...
I'm missing something, or maybe a lot of stuff...

Appreciate any help.

Thank you.


Message Edited by pyter on 02-27-2008 08:08 AM
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Observer xiaoxing_li
Observer
7,256 Views
Registered: ‎09-03-2008

Re: Modified Slideshow Example (512MB Dual Rank DDR) will only display small bitmaps

Hello,I am also stuck in reading files from flash drive(sysace cf ),have you got this problem solved yet? Does it has any relevance to the FAT16 file format? I found that it could read 16K which just the size of a cluster(including 32 sector) and then jump to the start of the program ……

  

thank you for you help!  

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