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mdakram140
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Registered: ‎07-02-2014

No response from the SGMII IP core via MDIO

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Hi all,

 

we are trying to connect custom mac controller which has GMII interface to SGMII IP core and then to Ethernet phy on the custom board. we are using VCU118 fpga kit.

 

the phy address we are giving is 5'b10000, we have enabled input and external management interface and connected to Ethernet phy. mdio from mac seems to working correctly as we are able to read the id code from the ethernet phy. but we are not able to get the response the SGMII ip core.

 

trying to do write and read

 

MSS_MAC_write_phy_reg
                (g_mac,
                    16,
                    0,
                    0x20
                );

        phy_val = MSS_MAC_read_phy_reg
                        (
                            g_mac,
                            16,
                            0
                        );

but we are getting response as all zeros...  not exactly sure why we are not getting the response from the SGMII ip core.  please let us what is the issue

 

Thanks

 

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mdakram140
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Registered: ‎07-02-2014

issue is resolved now

the mistake was in the gui the DRP clk was set as 50 mhz and the independent clk from outside i was giving as 200 mhz. since i am using ultrascale + device drp clk in the gui and independent clk from outside be same.

 

after the change sgmii registers are now respinding and resetdone signal is asserted.

 

thank you

 

View solution in original post

sgmii.PNG
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8 Replies
nanz
Moderator
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2,037 Views
Registered: ‎08-25-2009

Hi @mdakram140,

 

What is your MDC clock? Is it stable? Have you tried to access other registers and what do you read back?


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mdakram140
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Registered: ‎07-02-2014

Hi

Thanks for the reply,


MDC  clk is 1.25 Mhz , it is stable and we are able to write and read the Ethernet phy registers but when we are trying to  write and read the sgmii ip core registers it is not working as expected.

we have give Sgmii ip core address as 5'b10000 and ethernet phy on the custom board also we have connected such that address is 5'b10000.


we are trying to read the registers

register address

0                                  Register 0:                Control Register
1                                  Register 1:                Status Register
2,3                               Registers 2 and 3:     PHY Identifiers


we are not getting defaults values as mentioned in the document. for the above registers when we read


it is returned                                                  

register address                                              response

0                                  Register 0:                Control Register  (output all 1s)
1                                  Register 1:                Status Register   (all zeros)
2                              Registers 2      PHY Identifiers  (output all 1s)

3:                               register 3 -        (all zeros)

 

what can be the issue ??? 

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mdakram140
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Registered: ‎07-02-2014

actually it is returning all ones...

 

it is returned                                                  

register address                                              response

0                                  Register 0:                Control Register  (output all 1s)
1                                  Register 1:                Status Register   (output all 1s)
2                              Registers 2      PHY Identifiers  (output all 1s)

3:                               register 3 -        (output all 1s)

 

what can be the issue ???

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allanherriman
Mentor
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Registered: ‎01-08-2012

@mdakram140I'm curious: how have you connected your MDIO master (which I guess is inside your custom MAC) to the two MDIO slaves, one slave inside the SGMII core in the FPGA and one slave in the PHY outside the FPGA?

Can you post your HDL source, etc. or draw a picture or something like that ?

 

Does the SGMII core have all the correct clocks applied (and they are running) ?

Is it being held in reset?

 

 

EDIT: "reading all ones" is what you would expect when there isn't a slave there.  It could be caused by having the address wrong, etc.

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mdakram140
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Registered: ‎07-02-2014

Hi

thanks for the response

 i have instantiated the sgmii ip core in this way

 

                                           
GMII_Block_PMA_0_wrapper GMII_Interface_GEM0_inst(

                .independent_clock_bufg_0            (independent_clock_200),
 
   
                .gtpowergood_0                        (gtpowergood_0_out),
                .gtrefclk_in_0_clk_n                (gtrefclk_in_0_clk_n_in),    // Differential -ve of reference clock for MGT: very high quality.
                .gtrefclk_in_0_clk_p                (gtrefclk_in_0_clk_p_in),    // Differential +ve of reference clock for MGT: very high quality.
                .gtrefclk_out_0                        (),
                
                .sgmii_0_rxn                        (sgmii_0_rxn_in),            // Differential -ve for serial reception from PMD to PMA.
                .sgmii_0_rxp                        (sgmii_0_rxp_in),            // Differential +ve for serial reception from PMD to PMA.
                .sgmii_0_txn                        (sgmii_0_txn_out),            // Differential -ve of serial transmission from PMA to PMD.
                .sgmii_0_txp                        (sgmii_0_txp_out),            // Differential +ve of serial transmission from PMA to PMD.


                .gmii_isolate_0                        (),
                
                .gmii_pcs_pma_0_rx_dv                (fab_mac0_rx_dv_sync),
                                .gmii_pcs_pma_0_rx_er                (fab_mac0_rx_er_sync),
                                .gmii_pcs_pma_0_rxd                    (fab_mac0_rxd_sync),
                                
                                .gmii_pcs_pma_0_tx_en                (fab_mac0_tx_en_sync),
                                .gmii_pcs_pma_0_tx_er                (fab_mac0_tx_er_sync),
                                .gmii_pcs_pma_0_txd                    (fab_mac0_txd_sync),
                                
//                .sgmii_rx_clk                        (sgmii_rx_clk),
//                .sgmii_clk                            (sgmii_clk),

                
                .sgmii_clk_en_0                     (sgmii_clk_en_0),
                .sgmii_clk_f_0                      (sgmii_clk_f_0),
                .sgmii_clk_r_0                      (sgmii_clk_r_0),
                .sgmii_rx_clk_en_0                  (sgmii_rx_clk_en_0),
                .sgmii_rx_clk_f_0                   (sgmii_rx_clk_f_0),
                .sgmii_rx_clk_r_0                   (sgmii_rx_clk_r_0),

                .mdc_0                                (fab_mdio0_mdc_h2f),        // from GEM
                
                .mdio_i_0                            (fab_mdio0_out_h2f),                    
                .mdio_o_0                            (fab_mdio0_in_f2h),
                .mdio_t_0                            (),
                .mdio_t_in_0                        (fab_mdio0_oe_h2f),  // check important going to ext_t_in   

             

                .ext_mdc_0                            (phy_mdc),   // clk to external phy
                .ext_mdio_i_0                        (ext_mdio_i_0),
                .ext_mdio_o_0                        (ext_mdio_o_0),
                .ext_mdio_t_0                        (ext_mdio_t_0),
                


                
            //    .mdio_pcs_pma_0_mdio_io                (mdio_from_gem),     // from GEM
                                
                .phyaddr_0                            (phy_address),                  //5'b10000
                
               
            //    .ext_mdio_pcs_pma_0_mdio_io            (phy_mdio),   // mdio to external phy
                
                .configuration_valid_0                (1'b0),
                .configuration_vector_0                (5'b00000),
                

                .an_adv_config_val_0                (1'b0),
                .an_adv_config_vector_0                (16'h0000),
                .an_interrupt_0                        (Autonegotiation_interrupt),
                .an_restart_config_0                (1'b0),

                .speed_is_100_0                        (fab_mac0_speed_mode[0]),
                .speed_is_10_100_0                    (~fab_mac0_speed_mode[1]),

                .signal_detect_0                    (1'b1),
        //        .reset_0                            (fab_mgpio_out_h2f[1]),
        .reset_0                            (rst_sgmii_core),
        
                .resetdone_0                        (resetdone_frm_gtz),
                .status_vector_0                    (status_vector_0),
                .mmcm_locked_out_0                    (mmcm_locked_out_0_out),
                .pma_reset_out_0                    (pma_reset_out_0_out),

                .rxuserclk2_out_0                    (rxuserclk2),
                .rxuserclk_out_0                    (recovered_clk),
                .userclk2_out_0                        (usrclk_tx),
                .userclk_out_0                         ()
    );

 



        IOBUF  mdio ( .T(!ext_mdio_t_0), .I(ext_mdio_o_0), .O(ext_mdio_i_0), .IO(phy_mdio) );

 

 vio_1 vio_phy_address(
                        .clk            (clk_in_reference),
                        .probe_out0     (phy_address)
   );
   
vio_2 reset_to_core(
   .clk             (clk_in_reference),
   
   .probe_out0      (rst_sgmii_core)
   );

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mdakram140
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Registered: ‎07-02-2014
I have seen that the resetdone signal is not going high.. is it the issue ??? what can be the reason any suggestions??
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mdakram140
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Registered: ‎07-02-2014

issue is resolved now

the mistake was in the gui the DRP clk was set as 50 mhz and the independent clk from outside i was giving as 200 mhz. since i am using ultrascale + device drp clk in the gui and independent clk from outside be same.

 

after the change sgmii registers are now respinding and resetdone signal is asserted.

 

thank you

 

View solution in original post

sgmii.PNG
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paul.mnt
Observer
Observer
1,322 Views
Registered: ‎05-10-2013

If anybody is still facing this issue, note that there is typo in the VCU118 Schematic (HW-U1-VCU118_REV2_0_SCHEMATIC_7-14-2017.pdf):

On page 52 the PHY address is reported as 5'b0 1111, however, the address at reset, based on the strap resistors is 5'b0 0011.

Hope this helps!

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