cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Robert-Huang
Visitor
Visitor
478 Views
Registered: ‎07-22-2021

ORAN IF IP example design bitstream build fail

Jump to solution

Hello,

  In Vivado, I call the ORAN IF IP and open the example design.

  I try to build the bitstream, and I get the following error.

 example design & error.PNG

I expect the example design should come without an error, and I think the problem is the setting of package pin (as shown in the following figure).

Package pin.PNG

  May I ask how to set up the package pin?

  We are using board ZCU208.

Many thanks

Robert

  

 

 

 

0 Kudos
1 Solution

Accepted Solutions
xud
Xilinx Employee
Xilinx Employee
315 Views
Registered: ‎08-02-2007

@Robert-Huang 

If you have a look at PG370 chapter 4 Using the Example System in IP Integrator, it only shows two flows :

Run Block Automation
1. Open an IP integrator block design (BD) canvas.
2. Insert a O-RAN Radio IF IP on the canvas. A box appears on the upper left of the IP
integrator design viewer.
3. Select the box and run the block automation for the O-RAN Radio IF.
Custom Flows Using Tcl (used in the blog)
The Vivado Design Suite command line interface uses Tcl, which offers a means to extend the
design. Full details are hosted on GitHub;

Open IP example design is not there. This design doesn't contain processor or Ethernet IP. Even through you can generate xsa, you won't have a way to configure it (rely on PS) or receive/transfer data(rely on Ethernet interface).

But you can run simulation, that's why I mentioned it's only for simulation. 

For Block Automation design, yes, it can be run on board. 

View solution in original post

0 Kudos
7 Replies
xud
Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎08-02-2007

@Robert-Huang 

The constraints are only generated if you select ZCU102 board or ZCU111 board, and then add ORAN IP to a block design, run block automation.

After the design is generated, you can check the clock, reset, LED, DIP switch locations on ZCU208 board, and use it to replace the LOC constraint in ZCU102/ZCU111 board constraint file.

0 Kudos
Robert-Huang
Visitor
Visitor
395 Views
Registered: ‎07-22-2021

I've tried selecting the board ZCU111, and the rest of the procedure is the same as before, but I still get the same error message (as shown below):

Error msg ZCU111.png

Although this time, the IO ports are automatically assigned by the example design (as shown below):

ZCU111 IO ports.png

 This makes me more confused on where the problem is.

    Is there something wrong with the io ports, or the root cause is in somewhere else?

Thanks

Robert 

0 Kudos
xud
Xilinx Employee
Xilinx Employee
381 Views
Registered: ‎08-02-2007

@Robert-Huang 

Can you try with a linux machine? It might be relate to  window OS path limit.

In the meantime, can you share your ORAN IP configuration, and let me know Vivado version? I will try to reproduce the problem at my end.

0 Kudos
Robert-Huang
Visitor
Visitor
361 Views
Registered: ‎07-22-2021

Hi, 

It would take some time to change to Linux environment, but I think the problem should be solved in window environment as well.

For the ORAN IP configuration, as the description above , I just call out the ORAN IF IP, and generate the example design, no additional actions are taken.

The build error then occurs as the picture shown above.

For the Vivado version, we're using 2020.02.

 

Thanks

0 Kudos
xud
Xilinx Employee
Xilinx Employee
351 Views
Registered: ‎08-02-2007

@Robert-Huang 

Did you run block automation or using Open IP example design?

- Open IP example design : Don't contain LOC constraint, which is only for simulation

- Block Automation : can be run on board.

Please refer to Design Generation of blog https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/ORAN-wireless-xorif-hardware-demonstration/ba-p/1254509

And then generate the design, see if you can run through implementation. 

0 Kudos
Robert-Huang
Visitor
Visitor
327 Views
Registered: ‎07-22-2021

Hi,

 I was trying the method "Open IP example design", may I ask what do you mean by saying it is "only for simulation"?

 Does it mean that it is not designed for building out an .xsa file for running on board?

 As for the other method "Block Automation", can I think of it as another example design that can be run on board?

0 Kudos
xud
Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎08-02-2007

@Robert-Huang 

If you have a look at PG370 chapter 4 Using the Example System in IP Integrator, it only shows two flows :

Run Block Automation
1. Open an IP integrator block design (BD) canvas.
2. Insert a O-RAN Radio IF IP on the canvas. A box appears on the upper left of the IP
integrator design viewer.
3. Select the box and run the block automation for the O-RAN Radio IF.
Custom Flows Using Tcl (used in the blog)
The Vivado Design Suite command line interface uses Tcl, which offers a means to extend the
design. Full details are hosted on GitHub;

Open IP example design is not there. This design doesn't contain processor or Ethernet IP. Even through you can generate xsa, you won't have a way to configure it (rely on PS) or receive/transfer data(rely on Ethernet interface).

But you can run simulation, that's why I mentioned it's only for simulation. 

For Block Automation design, yes, it can be run on board. 

View solution in original post

0 Kudos