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Newbie andrew.lees
Newbie
8,483 Views
Registered: ‎12-10-2007

PCI core simulation problems

I am attempting to simulate logiPCI core and I am unable to get the core to stop switching the trdy_IO & devsel_IO lines between 1 and 0.  This makes it impossible to initiate any transactions on the bus.  I am unsure if this is a problem with my testbench or a configuration problem with the core.  I am using Modelsim version 6.3.
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3 Replies
Xilinx Employee
Xilinx Employee
8,470 Views
Registered: ‎08-07-2007

Re: PCI core simulation problems

Hi,

Based on what you said below it sounds like in your simulation you are seeing the core toggle TRDY# and DEVSEL# constantly? The only time the core will assert DEVSEL# is when it is the target of a bus transaction initiatied by another master. Once the core asserts DEVSEL# it will then assert TRDY# when the user asserts S_READY.

Can you get the default simulation that comes with the core to simulate properly? If so maybe take that as a starting point and intergrate your testbench in place of it and see if you can find where the break down is. Also if you want to respond and attach a screen shot of what you are seeing that would help me get an idea of whats going on. Show the bus signals and most of the S_* and M_* signals on the user app side if you can.

Regards,
John
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Newbie andrew.lees
Newbie
8,448 Views
Registered: ‎12-10-2007

Re: PCI core simulation problems

John,
 
Your previous assumptions are correct although I have since made progress.  I am attempting to configure the core, all transactions on the screen shot are either configuration reads or writes with the exception of the final transaction which is a memory read.  You will notice that the core does not respond to the conf reads with the exception of the first time and even then appears to remove data from the bus before the end of the transaction.  I'm reasonably sure that the pci signals are correct but unsure about the m_ and s_ signals.
 
This design includes a test bench, PCI core and user application.
 
Thanks for your help.
 
 
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Xilinx Employee
Xilinx Employee
8,391 Views
Registered: ‎08-07-2007

Re: PCI core simulation problems

Hi Andrew,

I realize this is kind of late in response, so maybe you have figured it out by now, but at the same time I don't see anything obviously wrong in the picture. However, my theory is that you appear to have some contention on the AD lines and I wonder if that is being cased in the TB. To me it seems like the core is trying to drive the data, but its in contention to something else. Do you have more than one core in this simultion. If so coudl the other one also be responding?

-John
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