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Registered: ‎10-10-2008

PHYSTATUS does not deassert after the reset sequence

Hi All,


I am trying to simulate the GTP_DUAL_FAST smart model for vertex 5 device for PCIe device.  The PMA PLL is locked and all the clocks and resets behave as per spec.  The issue is with PHYSTATUS which does not deassert after the reset sequence causing our LTSSM state machine to hang.  The PHYSTATUS always remains high and RXSTATUS[2:0]=0.  The TXDETECTRX is 0 while TXELECIDLE is 1.  As of now both RX and TX differential lines are inactive and RXRECCLK is 0.  RXRECCLK is tied to RXUSRCLK and RXPOWERDOWN[1:0]=tied to ground.


Please help me understand what will cause the PHYSTATUS not to toggle and hanging of the state-machine




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