05-13-2009 02:30 PM
I've been working with the RapidIO core and the Virtex5 processor on the ML505 EVM board. I've been able to successfully simulate and test the RapidIO hardware using a loop back on the SMA connects (after some code modifications to move it to GTP port 1 rather port 0 as it comes preconfigured). I can send data using the DIP switches/push switches and verify that things are working using ChipScope Pro.
My next task is to connect this to a DSP board that has built in RapdIO peripheral hardware. After getting things configured on both ends the Link LEDs are as follows:
port _initialized = good (on)
lnk_rrdy_n = good
lnk_trdy_n = good
pll_locked = good
lnk_porterr_n = off (no error)
mode_sel = on (datasheet says this is 4x eventhough I am using only 1 lane and not 4x serial so either this is wrong in the IP code or I am misunderstanding what this means)
My questions are:
1. From the LEDs it seems everything would be good. However whenever I send a message either from or to the DSP nothing happens on either end to illustrate data has been sent/received. What signals should I inspect at a low level (possibly in the PHY) that would indicate a message has been received or an error has occurred?
When the DSP sends a request to the FPGA it errors out with a PKT_RESPONSE_TIMEOUT. The DEVICE_ID's match. In fact they are both the same, perhaps that is a problem?
Any other suggestions would be appreciated,
06-17-2009 08:15 AM
I used a TI DSP C6474. The board has an advanced Mezzanine Connector (AMC) that has the Rapid I/O connections coming out, so we had to make an adapter board to connect between the DSP board and the Virtex SMA connectors.
I didn't have to make too many changes to the Rapid I/O core to get some data transfer. The changes I've listed above where the most significant ones. The other change was the DSP memory address for the NWRITE instruction. After that I could use the DIP switches and push buttons to transfer some data accross. One thing I did have to do was to decrease the link rate to 1.25 GBaud since our cable lengths where quite lengthy. This can be done in the core generator.
06-18-2009 01:18 AM
First of all, you must create a project with the help of Core Generator. There is a special script that create an ISE project or you can manually create this project, adding files that have been created by Core Generator. In ISE Project Navigator you must choose Simulation and you can simulate project using ModelSim.
Fore RapidIO Core you can get documentation, read it.
06-24-2009 12:44 AM - edited 06-24-2009 02:27 AM
Hi. Can you reccomend me what signal, clocks and ports must be added to ChipScope Pro in TRIGGER PORTS AND NET CONNECTIONS to verify SRIO example project for ML505 in proper way.
Thanks a lot.