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sandeepnvp
Visitor
Visitor
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Registered: ‎08-30-2019

Required IBIS model file for Zync-7000 with MIO pins operating at 3V3 rail

Hi,

I am trying to perform SI analysis on a 4 channel Automotive ethernet board (custom build daughter card) with FMC connector to be mounted on Zync-7000 evaluation board (ZC702 EVALUATION PLATFORM HW-Z7-ZC702) with FPGA part number (XC7Z020-CLG484). 

In order to perform this simulation I will be required with IBIS model file for this FPGA , which I got it from Xilinx Docnav app. But the issue is, this IBIS model file contains MIO pins configured as "HSTL_I_18_F_PSMIO" that are connecting with ethernet PHY RGMII lines on daughter card which is operating at 3V3 supply lines. 

So I would like to request through this forum to Xilinx users and support team to help me by provide an IBIS file in which FPGA MIO pins are configured at 3V3 supply lines.

Below are the images attached highlighting what model file is configured for that is available in Xilinx DocNav app.

sandeepnvp_0-1614234160481.jpegsandeepnvp_1-1614234209791.jpeg

 

Ethernet PHY pins required to be assigned with  MIO pins on FPGA.

sandeepnvp_2-1614234220676.jpeg

thanks,

Sandeep p

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nanz
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226 Views
Registered: ‎08-25-2009

Hi @sandeepnvp ,

To comment on the ethernet side, RGMII v3.3 is not supported on Zynq as it's hard to meet timing. 

If you still require a IBIS sim model on the MIO, I will need to move your thread to the appropriate forum board for further assistance. Please let me know. 


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