05-28-2014 12:17 PM
This might possibly be a beginner question.
I'm trying to use the XM104 daughtercard with the VC707 board.
The clock from the Si570 is being routed to MGT_BANK_118,
while the dataport 0 (which is the SMA port 0) is located on MGT_BANK_119.
I'm using the example design from the core catalog, which seems to be using the QPLL.
I've tried connecting the clocks from FMC1 HPC GBT_CLK1, through IBUFDS_GTE2,
to the .GTNORTHREFCLK0 in GTXE2_COMMON. An also changed QPLLREFCLKSEL to 3.
This change doesn't seem to work yet.
Is there many more things I should be changing?
Thank you in advance for the help!
05-28-2014 11:01 PM - edited 05-28-2014 11:09 PM
The way you have sourced the clock i.e. from Si570 of XM104 to fmc1_hpc_gbtclk1_m2c_c_p to refclk0 of quad118 is correct. The QPLLREFCLKSEL attribute value is also correct.
Can you first make sure that you simulate the design and ensure the correct operation.
Later we discuss about hardware debugging.
05-28-2014 11:02 PM
"This change doesn't seem to work yet." Can you elaborate what is not working?
Can you check the clock at the TXUSRCLK ports to confirm if the clock is being received or not.
Note there is no need to change these settings manually. the coregen tool "7 series FPGA transeceiver wizard " has the option for selecting adjacent tile clocks. check screenshot below.